AM572x crash inside H264 codec process call

Apoorva Nagarajan

Other Parts Discussed in Thread: SYSBIOS, AM5728

Hi,

I have simple encoder and decoder application running on IPU2 (sysbios) directly. My application uses the TI HDVICP encoder and decoder. At times, I observe a crash inside the codec process call. I am running this application using CCS and have obtained the following stack trace.

[t=0x00000001:216346d7] ti.sdo.fc.ires.hdvicp2: [+E] ti_sdo_fc_ires_hdvicp_HDVICP2_w[t=0x00000001:21c3584d] ti.sdo.[t=0x00000001:21f682ed] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1078: E_hardFault: FORCED
ti.sysbios.family.arm.m3.Hwi: line 1078: E_hardFault: FORCED
[t=0x00000001:22cce0b1] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: f1016017
ti.sysbios.family.arm.m3.Hwi: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: f1016017
Exception occurred in background thread at PC = 0x8017c124.
Core 0: Exception occurred in ThreadType_Swi.
Swi name: {unknown-instance-name}, handle: 0x80610678.
Swi stack base: 0x8060c570.
Swi stack size: 0x3000.
R0 = 0xf1a00204 R8 = 0x00000006
R1 = 0x00000000 R9 = 0x00000000
R2 = 0xf1016013 R10 = 0x00000000
R3 = 0x8060f80c R11 = 0xffffffff
R4 = 0x00000000 R12 = 0x00000010
R5 = 0x00000001 SP(R13) = 0x8060f2f8
R6 = 0x80610878 LR(R14) = 0x8017bdfd
R7 = 0x0000002e PC(R15) = 0x8017c124
PSR = 0x61000000
ICSR = 0x00435803
MMFSR = 0x00
BFSR = 0x82
UFSR = 0x0000
HFSR = 0x40000000
DFSR = 0x00000000
MMAR = 0xf1016017
BFAR = 0xf1016017
AFSR = 0x00000000
Terminating execution...

Apart from this, I have followed the instructions provided in the below link

processors.wiki.ti.com/.../BIOS_FAQs

I get a call trace as below

What could the issue be? Any inputs provided would be very valuable.

Thank you.

Regards,

Apoorva

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

I have notified the RTOS team to look at this.

0 Paula Carrillo over 9 years ago

TI__Mastermind 39300 points

Hi Apoorva, from where do you get HDVIC H264 video codecs? are you trying to run any of our demos or this is your own video codec demo?. Trying to see if there is any way to reproduce it..
thanks,
Paula

0 Apoorva Nagarajan over 9 years ago in reply to Paula Carrillo

Intellectual 505 points

Hi Paula,

I have taken the HDVICP H264 codecs from PSDK 02_00_00_00. I am not using the TI codec demos. I have written a simple application on IPU, which makes codec engine calls.

This is the way I am testing my application:
1. I am running the application through CCS
2. Stop the board boot at u-boot level
2. Connect IPU2_C0 and load the application
3. A15 is not connected (There is no IPC happening)
4. Run the application on IPU2_C0

Additionally, I observe that I had enabled all the logs while running the application. I don't see this issue when the logs are disabled. Is this some kind of timing issue?

Regards,
Apoorva

0 Paula Carrillo over 9 years ago in reply to Apoorva Nagarajan

TI__Mastermind 39300 points

Hi Apporva, yes it seems a timing issue. I will try to find someone in TI familiar with PSDK 02_00_00_00

thank you,

Paula

0 Gajanan Maske over 9 years ago in reply to Paula Carrillo

Expert 2325 points

Hi Appova,

Is your application is aligned with standalone test application provided along with the Codec package ??

Regards

Gajanan

0 Apoorva Nagarajan over 9 years ago in reply to Gajanan Maske

Intellectual 505 points

Hi Gajanan,

Is there a standalone test application along with the Codec package? I don't find any. Can you please point me to the test application?

I have used viddec3test and videnc2test applications present in PSDK as reference.

Regards,
Apoorva

0 Gajanan Maske over 9 years ago in reply to Apoorva Nagarajan

Expert 2325 points

Hi Apoorva,

I had shared you the client application code to your email-id. Please refer it.

Regards
Gajanan

0 Apoorva Nagarajan over 9 years ago in reply to Gajanan Maske

Intellectual 505 points

Gajanan/Paula,

We are facing performance issue with the TI IVAHD h264 codecs. For the exact description, refer to this link: e2e.ti.com/.../536825

We believe that we are facing this issue because we have replaced tiler memory with raw memory. When we referred to your sample application, we see that you have initialized tiler memory and allocating memory from tiler. But that part of the code is in the form of a built library (not built for AM5728)

As our application is standalone running on M4, we cannot use A15 to allocate tiler memory as done in DCE. Can you either provide us the tiler memory library built for AM5728 or the source code of that library?

Regards,
Apoorva

0 Gajanan Maske over 9 years ago in reply to Apoorva Nagarajan

Expert 2325 points

Hi Apoorva,

I had shared you the sample applicaton code to use the tiler library. I hope it will be useful for your developement.

Regards

Gajanan

0 Apoorva Nagarajan over 9 years ago in reply to Gajanan Maske

Intellectual 505 points

Hi Gajanan,

I went through the sample application. From what I could gather, to use TILER memory for encoder input buffers, YUV data is read onto raw memory and that data is byte-by-byte transferred to the TILER memory before giving it to the encoder. Does this run at 60fps for 1920x1080 resolution?

If we were to use this in a system, say, capture YUV data then encode the data, should the capture also happen on TILED memory? Is it possible to capture video in a TILED fashion?

Regards,
Apoorva

0 Gajanan Maske over 9 years ago in reply to Apoorva Nagarajan

Expert 2325 points

Hi Apoorva,

This is the standalone test-application which will be used by file-based encoding. To get the real time ,yes Capture should happen TILED memory. Please refer the SDK/RDK provided for better clarity which can support real time performance using these techniques.

Regards
Gajanan

0 Apoorva Nagarajan over 9 years ago in reply to Gajanan Maske

Intellectual 505 points

Hi Gajanan,

As you know, I have a simple encoder-decoder application running on m4 directly. I am trying to use tiler memory instead of raw memory. To do this, I have referred to the sample application which was shared.

I have done the following to enable tiler:

1. Program the TILER PAT
/*---------------------------------------------------------------------------------------*/
/* Tiler is mapped to following physical container addresses: */
/* TILE8_PHY_ADDR - 0xa800 0000 -> 0xb000 0000 */
/* TILE16_PHY_ADDR - 0xb000 0000 -> 0xb800 0000 */
/* TILE32_PHY_ADDR - 0xb800 0000 -> 0xc000 0000 */
/* TILEPG_PHY_ADDR - 0xb800 0000 -> 0xc000 0000 */
/* Tiler32 & TilePG are overlayed with assumption that Tile32 is not */
/* used */
/*----------------------------------------------------------------------------------------*/

*(int *)(0x4E000440) = 0x07070605;
*(int *)(0x4E000444) = 0x07070605;
*(int *)(0x4E000448) = 0x07070605;
*(int *)(0x4E00044C) = 0x07070605;

*(int *)(0x4E000460) = 0x80000000;

*(int *)(0x4E000480) = 0x00000003;
*(int *)(0x4E0004C0) = 0x0000000B;
*(int *)(0x4E000504) = 0x3FFF20E0;
*(int *)(0x4E00050C) = 0x8510F010;

2. Added a large page in IPU MMU configuration to map 0x60000000 to 0xA0000000

/*---------------- Setup the UNICACHE MMU -----------------*/
/*Large Page Translations */
/* Logical Address */
regAddr = IPU_MMU_CFG;
regAddr += 0x800;
WR_MEM_32(regAddr, 0x40000000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x60000000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x80000000); regAddr += 0x4;
WR_MEM_32(regAddr, 0xA0000000); regAddr += 0x4;

/* Physical Address */
regAddr = IPU_MMU_CFG;
regAddr += 0x820;
WR_MEM_32(regAddr, 0x40000000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x40000000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x80000000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x60000000); regAddr += 0x4;

/* Policy Register */
regAddr = IPU_MMU_CFG;
regAddr += 0x840;
WR_MEM_32(regAddr, 0x00000007); regAddr += 0x4;
WR_MEM_32(regAddr, 0x00000007); regAddr += 0x4;
WR_MEM_32(regAddr, 0x000B0007); regAddr += 0x4;
WR_MEM_32(regAddr, 0x00000007); regAddr += 0x4;

Now if I access memory starting from 0xA0000000, I should be able to access the tiler memory. But no success, I am not able to access memory from 0xA0000000.

Are there any other steps to initialize the TILER memory? Am I missing anything here? What could the issue be?

Also, can you provide steps to run the sample application that was shared?

Regards,
Apoorva

0 Gajanan Maske over 9 years ago in reply to Apoorva Nagarajan

Expert 2325 points

Hi Apoorva,

I am not sure the settings done currently. I will check & if something missing I will let you know.

Meanwhile I wanted to update you that the shared application code is holds true for NETRA(DM816x) and OMAP4. So the register changes & memory address need to be handled accordingly.

Regards

Gajanan

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AM572x crash inside H264 codec process call