AM335x pin Tri-state

Steve Deschryver

Other Parts Discussed in Thread: AM3354, TMDSICE3359

Dear,

I want to externally program a NOR flash connector to the SPI0 bus of the AM3354, this is only possible if the AM3354 is not driving the pins.

In the SPRUH73M datasheet (rev jan 2016) page 1158 I found that all resets sources except the TRSTz pin will put IOs in Tri-state.

Can you please confirm this, so if I pull the WARMRST (pin A10) continuous low I will be able to drive the SPI0 lines from an external device ?

Kind regards,

Steve

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Please post which pin numbers you are asking about, and processor case (ZCE or ZCZ).

0 Steve Deschryver over 9 years ago in reply to Biser Gatchev-XID

Expert 1115 points

SPI0_CLK A17
SPI0_DO B17
SPI0_DI B16
SPI0_CS0 A16
on an AM3354 ZCZ package

0 Biser Gatchev-XID over 8 years ago in reply to Steve Deschryver

TI__Guru**** 393215 points

Yes, these pins will be tri-stated while reset is asserted.

0 Steve Deschryver over 8 years ago in reply to Biser Gatchev-XID

Expert 1115 points

Ok thanks, I will order a SPI programmer now and test this.

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

Our customer wants that IOs are in a high impedance state with internal weak pull- down/pull-up resistors during a warm reset.

The internal pull- down/pull-up of each IO except some exceptions during a warm reset should accord with "BALL RESET STATE" in datasheet.

What are some exceptions?

The some exceptions will be described in Table 8-25 on TRM (SPRUH73P):

"(4) There are exception details in control module & PRCM registers which are captured in the register specifications in Chapter 8 and Chapter 9. This includes some pinmux registers which
are warm reset in-sensitive."

"(5) Some special IOs/Muxing registers like test, emulation, GEMAC Switch (When under reset isolation mode), etc related will not be affected under warm reset conditions."

If IOs/Muxing registers mean Pad Control Registers, which are the registers which are not affected under warm reset conditions?

Best regards,

Daisuke

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

I checked some IOs as examples using TMDSICE3359. Each of following IOs is only connected to J3 connector in TMDSICE3359.

- UART0_CTSn (E18)
- UART0_RTSn (E17)
- UART1_RTSn (D17)
- UART1_CTSn (D18)

Each of these IOs is "Z" in "BALL RESET STATE" but shows logic high during a warm reset in TMDSICE3359.

An active state of internal pull-down/pull-up resistors seems to maintain their current value throughout a warm reset.

Is an active state of all internal pull-down/pull-up resistors warm reset insensitive?

Our customer wants to avoid that IOs in their board is floating during a long-term warm reset.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

My new post is right here: e2e.ti.com/.../593673

Best regards,

Daisuke

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AM335x pin Tri-state