We use TLK105RHBR Ethernet PHY.
The Ethernet PHY is connected to CPU via GMII1_XXX signals and uses external
clock (25MHz) which also connected to CPU as reference clock. PHY address is 1.
We are trying to enable Ethernet in u-boot 2016-05, but it does not work.
we have done following changes:
board.c"
//Before
if (board_is_bone() || board_is_bone_lt() ||
board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else if (board_is_icev2()) {
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 1;
cpsw_slaves[1].phy_addr = 3;
} else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
...
//After
if (board_is_bone() || board_is_bone_lt() ||
board_is_idk() || board_is_costom()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
cpsw_slaves[0].phy_addr = 1;
} else if (board_is_icev2()) {
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 1;
cpsw_slaves[1].phy_addr = 3;
} else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
...
pinmux.c:
//Added
if (board_is_costum()) {
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_no_wp_pin_mux);
configure_module_pin_mux(nand_pin_mux);
configure_module_pin_mux(i2c1_pin_mux);
}
In DTS file the Ethernet configured following way:
&am33xx_pinmux {
pinctrl-names = "default";
...
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x110 ( PIN_INPUT | MUX_MODE0 ) /* (J15) gmii1_rxer.gmii1_rxer */
0x114 ( PIN_OUTPUT | MUX_MODE0 ) /* (J16) gmii1_txen.gmii1_txen */
0x118 ( PIN_INPUT | MUX_MODE0 ) /* (J17) gmii1_rxdv.gmii1_rxdv */
0x12c ( PIN_INPUT | MUX_MODE0 ) /* (K18) gmii1_txclk.gmii1_txclk */
0x130 ( PIN_INPUT | MUX_MODE0 ) /* (L18) gmii1_rxclk.gmii1_rxclk */
0x128 ( PIN_OUTPUT | MUX_MODE0 ) /* (K17) gmii1_txd0.gmii1_txd0 */
0x124 ( PIN_OUTPUT | MUX_MODE0 ) /* (K16) gmii1_txd1.gmii1_txd1 */
0x120 ( PIN_OUTPUT | MUX_MODE0 ) /* (K15) gmii1_txd2.gmii1_txd2 */
0x11c ( PIN_OUTPUT | MUX_MODE0 ) /* (J18) gmii1_txd3.gmii1_txd3 */
0x140 ( PIN_INPUT | MUX_MODE0 ) /* (M16) gmii1_rxd0.gmii1_rxd0 */
0x13c ( PIN_INPUT | MUX_MODE0 ) /* (L15) gmii1_rxd1.gmii1_rxd1 */
0x138 ( PIN_INPUT | MUX_MODE0 ) /* (L16) gmii1_rxd2.gmii1_rxd2 */
0x134 ( PIN_INPUT | MUX_MODE0 ) /* (L17) gmii1_rxd3.gmii1_rxd3 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J15) gmii1_rxer.gmii1_rxer */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J16) gmii1_txen.gmii1_txen */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J17) gmii1_rxdv.gmii1_rxdv */
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K18) gmii1_txclk.gmii1_txclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L18) gmii1_rxclk.gmii1_rxclk */
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K17) gmii1_txd0.gmii1_txd0 */
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.gmii1_txd1 */
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K15) gmii1_txd2.gmii1_txd2 */
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J18) gmii1_txd3.gmii1_txd3 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M16) gmii1_rxd0.gmii1_rxd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L15) gmii1_rxd1.gmii1_rxd1 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L16) gmii1_rxd2.gmii1_rxd2 */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L17) gmii1_rxd3.gmii1_rxd3 */
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* (M17) mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* (M18) mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
....
}
...
&mac {
active_slave = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
After booting u-boot I can read PHY registers see results below:
=> mii dump 1 0
0. (3100) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:2000) 0. 6,13 = b01 speed selection = 100 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)
=> mii dump 1 1
1. (786d) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:4000) 1.14 = 1 100BASE-X full duplex able
(2000:2000) 1.13 = 1 100BASE-X half duplex able
(1000:1000) 1.12 = 1 10 Mbps full duplex able
(0800:0800) 1.11 = 1 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0000) 1. 8 = 0 extended status
(0080:0000) 1. 7 = 0 (reserved)
(0040:0040) 1. 6 = 1 MF preamble suppression
(0020:0020) 1. 5 = 1 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0008) 1. 3 = 1 A/N able
(0004:0004) 1. 2 = 1 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0001) 1. 0 = 1 extended capabilities
=> mii dump 1 2
2. (2000) -- PHY ID 1 register --
(ffff:2000) 2.15- 0 = 8192 OUI portion
=> mii dump 1 3
3. (a211) -- PHY ID 2 register --
(fc00:a000) 3.15-10 = 40 OUI portion
(03f0:0210) 3. 9- 4 = 33 manufacturer part number
(000f:0001) 3. 3- 0 = 1 manufacturer rev. number
=> mii dump 1 4
4. (01e1) -- Autonegotiation advertisement register --
(8000:0000) 4.15 = 0 next page able
(4000:0000) 4.14 = 0 (reserved)
(2000:0000) 4.13 = 0 remote fault
(1000:0000) 4.12 = 0 (reserved)
(0800:0000) 4.11 = 0 asymmetric pause
(0400:0000) 4.10 = 0 pause enable
(0200:0000) 4. 9 = 0 100BASE-T4 able
(0100:0100) 4. 8 = 1 100BASE-TX full duplex able
(0080:0080) 4. 7 = 1 100BASE-TX able
(0040:0040) 4. 6 = 1 10BASE-T full duplex able
(0020:0020) 4. 5 = 1 10BASE-T able
(001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3
=> mii dump 1 5
5. (cde1) -- Autonegotiation partner abilities register --
(8000:8000) 5.15 = 1 next page able
(4000:4000) 5.14 = 1 acknowledge
(2000:0000) 5.13 = 0 remote fault
(1000:0000) 5.12 = 0 (reserved)
(0800:0800) 5.11 = 1 asymmetric pause able
(0400:0400) 5.10 = 1 pause able
(0200:0000) 5. 9 = 0 100BASE-T4 able
(0100:0100) 5. 8 = 1 100BASE-X full duplex able
(0080:0080) 5. 7 = 1 100BASE-TX able
(0040:0040) 5. 6 = 1 10BASE-T full duplex able
(0020:0020) 5. 5 = 1 10BASE-T able
(001f:0001) 5. 4- 0 = 1 selector = IEEE 802.3
But when we are doing ping or dhcp device can't connect to HOST.
Also we have tried to see packets with network sniffer and I do not see any ping
packets from device.
Please help to understand what we are doing wrong.