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AM335x DDR3 configuration

vasanth TP
Intellectual 460 points
Other Parts Discussed in Thread: AM3357, CODECOMPOSER

Dear Biser,

We have a custom board for AM3357 processor similar to EVM but slight difference in DDR3,

We used MT41K512M16HA-107 DDR3L device from Micron, We have routed DDR3L Signals as per BeagleBoneBlack. 

Only change is we have used 8Gb Device instead of 4Gb ( MT41K256M16HA-125 ).1258.Querye2e.zip

We are using Code Composer Studio Version: 6.1.3.00034 and XDS100V2 jtag Debuger to load BeagleBoneBlack .gel file ,
which we have used the values provided by MT41K512M16HA-107 datasheet.

Problem faced while modifing DDR Address 0x800000000 = < Value >, It is not only modifing Offset 0x0, it is also manuplating offset 0x4,0x8 and 0xC.
Please find the attached files for your reference ( Querye2e.zip )

1. BeagleBlack_400Mhz_4GbDDR.gel
2. AM335x_DDR_register_calc_tool.xls
3. Console_Output.txt ( outputed console prints on Code Composer )
4. MemoryBrowser.png ( manuplating other offset 0x4, 0x8 and 0xc )


With Regards,

Vasanth

  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    Dear Biser,

    We tried SDRAM_TIM_1=0x0AAAD4DB, SDRAM_TIM_2= 0X468F7FDA, SDRAM_TIM_3 = 0X501F88BF

    But it failed to read memory, ,

    When we tried to write on to the memory location it gave error, Please see the attached log for error 

    Fullscreen Console_Output1.txt Download 
    CortxA8: Output: ****  AM335x BeagleBlack Initialization is in progress .......... 
CortxA8: Output: ****  AM335x ALL PLL Config for OPP == OPP100 is in progress ......... 
CortxA8: Output: Input Clock Read from SYSBOOT[15:14]:  24MHz
CortxA8: Output: ****  Going to Bypass... 
CortxA8: Output: ****  Bypassed, changing values... 
CortxA8: Output: ****  Locking ARM PLL
CortxA8: Output: ****  Core Bypassed
CortxA8: Output: ****  Now locking Core...
CortxA8: Output: ****  Core locked
CortxA8: Output: ****  DDR DPLL Bypassed
CortxA8: Output: ****  DDR DPLL Locked
CortxA8: Output: ****  PER DPLL Bypassed
CortxA8: Output: ****  PER DPLL Locked
CortxA8: Output: ****  DISP PLL Config is in progress .......... 
CortxA8: Output: ****  DISP PLL Config is DONE .......... 
CortxA8: Output: ****  AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... 
CortxA8: Output: ****  AM335x DDR3 EMIF and PHY configuration is in progress......... 
CortxA8: Output: EMIF PRCM is in progress ....... 
CortxA8: Output: EMIF PRCM Done 
CortxA8: Output: DDR PHY Configuration in progress 
CortxA8: Output: Waiting for VTP Ready ....... 
CortxA8: Output: VTP is Ready! 
CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... 
CortxA8: Output: Setting IO control registers....... 
CortxA8: Output: EMIF Timing register configuration is in progress ....... 
CortxA8: Output: EMIF Timing register configuration is done ....... 
CortxA8: Output: PHY is READY!!
CortxA8: Output: DDR PHY Configuration done 
CortxA8: Output: ****  AM335x BeagleBlack Initialization is Done ****************** 


CortxA8: Trouble Writing Memory Block at 0x8000000 on Page 0 of Length 0x4: (Error -1065 @ 0x3D5A) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0) 
CortxA8: Trouble Writing Memory Block at 0x8000004 on Page 0 of Length 0x4: (Error -1065 @ 0x3D5A) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)

  • 0 in reply to vasanth TP
    TI__Guru**** 393215 points
    Is your DDR clock set to 400MHz? The timings I gave you are for 400MHz.
  • 0 in reply to vasanth TP
    TI__Guru**** 393215 points
    Have you done the software leveling routine? Please follow the wiki I posted above for step-by-step guidance.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    Dear Sir,


    Please find the link used for software leveling.
    processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

    Find the attached SlewOutput-BBB.txt is Codecomposer console output.
    We have followed the procedure which was provided by your earlier reply
    ( processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack ).
    No changes observed.


    By defalut OCP data widthe is 128 bit as queried by reading regiser OCP_CFG_VAL_1 Register. This register is read only.
    Can we have a option to change it to 32bit instead of 128bit.

    Board Info for your reference

    CPU : Am3357
    DDR3L : MT41k512M16HA-107 ( 1GByte Memory 0x80000000 - 0xBFFFFFFF ) 64 Meg x 16 x 8 banks

    Fullscreen SlewOutput-BBB.txt Download 
    [CortxA8] 
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
70

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
1

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06f | 0x005 |  0x03a  | 0x06a
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x137 | 0x000 |  0x09b  | 0x137
DATA_PHY_WR_DQS_SLAVE_RATIO    0x03a | 0x000 |  0x01d  | 0x03a
DATA_PHY_WR_DATA_SLAVE_RATIO   0x067 | 0x009 |  0x038  | 0x05e
***************************************************************
rd_dqs_range = 3a
fifo_we_range = 9b
wr_dqs_range = 1d
wr_data_range = 38

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06d | 0x005 |  0x039  | 0x068
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x133 | 0x000 |  0x099  | 0x133
DATA_PHY_WR_DQS_SLAVE_RATIO    0x056 | 0x000 |  0x02b  | 0x056
DATA_PHY_WR_DATA_SLAVE_RATIO   0x085 | 0x025 |  0x055  | 0x060
***************************************************************
rd_dqs_range = 1
fifo_we_range = 2
wr_dqs_range = e
wr_data_range = 1d

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06d | 0x005 |  0x039  | 0x068
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x133 | 0x000 |  0x099  | 0x133
DATA_PHY_WR_DQS_SLAVE_RATIO    0x062 | 0x003 |  0x032  | 0x05f
DATA_PHY_WR_DATA_SLAVE_RATIO   0x092 | 0x032 |  0x062  | 0x060
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 7
wr_data_range = d

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06e | 0x005 |  0x039  | 0x069
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x133 | 0x000 |  0x099  | 0x133
DATA_PHY_WR_DQS_SLAVE_RATIO    0x069 | 0x009 |  0x039  | 0x060
DATA_PHY_WR_DATA_SLAVE_RATIO   0x09d | 0x03b |  0x06c  | 0x062
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 7
wr_data_range = a

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06f | 0x005 |  0x03a  | 0x06a
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x131 | 0x000 |  0x098  | 0x131
DATA_PHY_WR_DQS_SLAVE_RATIO    0x072 | 0x012 |  0x042  | 0x060
DATA_PHY_WR_DATA_SLAVE_RATIO   0x0a1 | 0x041 |  0x071  | 0x060
***************************************************************
rd_dqs_range = 1
fifo_we_range = 1
wr_dqs_range = 9
wr_data_range = 5

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06d | 0x005 |  0x039  | 0x068
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x132 | 0x000 |  0x099  | 0x132
DATA_PHY_WR_DQS_SLAVE_RATIO    0x078 | 0x01a |  0x049  | 0x05e
DATA_PHY_WR_DATA_SLAVE_RATIO   0x0a9 | 0x04a |  0x079  | 0x05f
***************************************************************
rd_dqs_range = 1
fifo_we_range = 1
wr_dqs_range = 7
wr_data_range = 8

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06e | 0x005 |  0x039  | 0x069
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x133 | 0x000 |  0x099  | 0x133
DATA_PHY_WR_DQS_SLAVE_RATIO    0x078 | 0x021 |  0x04c  | 0x057
DATA_PHY_WR_DATA_SLAVE_RATIO   0x0b0 | 0x050 |  0x080  | 0x060
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 3
wr_data_range = 7

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06e | 0x005 |  0x039  | 0x069
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x131 | 0x000 |  0x098  | 0x131
DATA_PHY_WR_DQS_SLAVE_RATIO    0x078 | 0x025 |  0x04e  | 0x053
DATA_PHY_WR_DATA_SLAVE_RATIO   0x0b4 | 0x054 |  0x084  | 0x060
***************************************************************
rd_dqs_range = 0
fifo_we_range = 1
wr_dqs_range = 2
wr_data_range = 4

Optimal values not reached, rerunning program with new values...

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06d | 0x005 |  0x039  | 0x068
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x131 | 0x000 |  0x098  | 0x131
DATA_PHY_WR_DQS_SLAVE_RATIO    0x078 | 0x029 |  0x050  | 0x04f
DATA_PHY_WR_DATA_SLAVE_RATIO   0x0b6 | 0x057 |  0x086  | 0x05f
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 2
wr_data_range = 2

Optimal values have been found!!

***************************************************************
	The Slave Ratio Search Program Values are... 
***************************************************************
PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE	
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO    0x06d | 0x005 |  0x039  | 0x068
DATA_PHY_FIFO_WE_SLAVE_RATIO   0x131 | 0x000 |  0x098  | 0x131
DATA_PHY_WR_DQS_SLAVE_RATIO    0x078 | 0x029 |  0x050  | 0x04f
DATA_PHY_WR_DATA_SLAVE_RATIO   0x0b6 | 0x057 |  0x086  | 0x05f
***************************************************************

===== END OF TEST =====
    Regards,
    Vasanth

  • 0 in reply to vasanth TP
    TI__Guru**** 393215 points

    vasanth TP said:
    By defalut OCP data widthe is 128 bit as queried by reading regiser OCP_CFG_VAL_1 Register. This register is read only.
    Can we have a option to change it to 32bit instead of 128bit.

    No, this is fixed.

    Is this a single board or do you see the same behavior on multiple boards?

  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    Dear Sir,

    Thanks for your previous input to check the same in alternative board . We were able to sucessfully test ddr working.

    So we have taken the final values what we have fed in gel file ( etce timing1 , timing2 .... sdram_config).

    Modified in uboot source. Especially in ddr_defs.h and board.c file in board/ti/am335x/board.c

    Complied using arm-linux-gnueabi tool chain. We used am335x_boneblack_defconfig .

    We have fused MLO and u-boot.img to nand at 0x0 and 0x80000 offsets respectively.

    we followed the steps as provied in the below link 

    We expect to see some console message on  serial. But no messages have been printed.

    The only difference between bbb board and custom board is higher density bbb uses 512MB and custom board uses 1GB.

    Please find the gel file attached for which ddr was tested sucessfully.

    1. MLO file

    2. u-boot.img

    MLO & U-BOOT.zip

    Awaiting for your earliest reply.

    With Reards,

    Vasanth

  • 0 in reply to vasanth TP
    TI__Guru**** 393215 points
    I will ask the software team to comment. They will respond here. You are probably running into the board ID EEPROM check and hanging there.
  • 0 in reply to vasanth TP
    TI__Guru**** 170625 points
    Vasanth,

    Reading the e2e thread, it seems to me that your custom board is based on BeagleBoneBlack, not on AM335x EVM.

    Do you use TI PSDK 03_01_00_06? If yes, use am335x_evm_nandboot_config (not am335x_boneblack_defconfig). See the below wiki page for more info:

    processors.wiki.ti.com/.../Linux_Core_U-Boot_User's_Guide

    Regards,
    Pavel
  • 0
    TI__Guru**** 170625 points

    vasanth TP said:
    Problem faced while modifing DDR Address 0x800000000 = < Value >, It is not only modifing Offset 0x0, it is also manuplating offset 0x4,0x8 and 0xC.

    This is likely a configuration issue, i.e. double check the DDR data sheet against your configuration. You likely have a mismatch with respect to number of banks, column address bits, etc.

    processors.wiki.ti.com/.../Common_DDR_Issues

  • 0 in reply to Pavel Botev
    Intellectual 460 points

    Dear Pavel,

    As per your suggestion We have used UBOOT downloaded  from git.ti.com/ipnc-ti-uboot ( ipnc-rdk-ipnc-ti-u-boot-95c8de84.tar.gz ).

    configure for am335x_evm_nandboot_defconfig , used arm-linux-gnueabii toolchin. ensured to modify ddr_defs.h to desired values such timing1 ... sdram_config etc..

    Downloaded 

    1. MLO to nand offset 0x0

    2. u-boot.img to nand offset 0x80000.

    Still we are not able to see any console output on UART0. Kindly advice .

    Regards

    Vasanth

  • 0 in reply to vasanth TP
    TI__Guru**** 170625 points

    Dear Vasanth,

    vasanth TP said:
    As per your suggestion We have used UBOOT downloaded  from git.ti.com/ipnc-ti-uboot ( ipnc-rdk-ipnc-ti-u-boot-95c8de84.tar.gz ).

    My suggestion? When and where I made such suggestion?

    What I suggest you now is to use the u-boot coming with the latest AM335x TI PSDK

    ti-processor-sdk-linux-am335x-evm-03.01.00.06/board-support/u-boot-2016.05


    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 460 points

    Dear Pavel / Biser,

    We are downloading the latest linux SDK, mean while we are trying to debug starter ware 02.00.01.01 BOOT.elf.

    We found it was getting hang during communicating with PMIC (TPS65910A3) via I2C.

    We have connected PMIC to processor as per EVM schematic 1.6A.

    Please kindly advice.

    Regards

    Vasanth

  • 0 in reply to vasanth TP
    TI__Guru**** 393215 points
    Starterware is supported on a different forum: e2e.ti.com/.../790.aspx Please ask all Starterware related questions there.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 460 points

    Dear Biser,

    We posted our quire (e2e.ti.com/.../556047) in the above said post but we have not got any reply  till now.

    Regards

    Vasanth 

  • 0 in reply to Pavel Botev
    Intellectual 460 points

    Dear Pavel,

    We have download ti-processor-sdk-linux-am335x-evm-03.01.00.06/board-support/u-boot-2016.05 version.

    Cross compiled using arm-linux-gnueabi and configured am335x_nandboot_defconfig board and we are able to boot to promt.

    But we getting error as " - No Valid Environment Area found".We have modified CMD_ENV to reside in NAND address 0x1c0000.

    Please find the attached log file. Awaiting for your response.

    Fullscreen QueryLog.txt Download 
    U-Boot SPL 2016.05-00118-gabc6b2a-dirty (Nov 30 2016 - 20:14:22)
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured
Trying to boot from NAND
The Expected Linux image was not found. Please check your NAND configuration.
Trying to start u-boot now...


U-Boot 2016.05-00118-gabc6b2a-dirty (Nov 30 2016 - 20:14:22 +0530)

       Watchdog enabled
I2C:   ready
DRAM:  1 GiB
NAND:  256 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Error - No Valid Environment Area found
*** Warning - bad CRC, using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net:   wait_for_user_access Timeout
wait_for_user_access Timeout
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eth0: ethernet@4a100000
Warning: usb_ether MAC addresses don't match:
Address in SROM is         de:ad:be:ef:00:01
Address in environment is  68:c9:0b:75:13:65
, eth1: usb_ether
Press SPACE to abort autoboot in 2 seconds
=>

    Regards,

    Vasanth

  • 0 in reply to vasanth TP
    TI__Guru**** 170625 points

    vasanth TP said:
    Cross compiled using arm-linux-gnueabi

    The right cross compiler is arm-linux-gnueabihf.

    ti-processor-sdk-linux-am335x-evm-03.01.00.06/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/arm-linux-gnueabihf-gcc-5.3.1

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 460 points

    Dear Pavel,

    We used the above said compiler , there is no changes. Kindly let us know how to disable usb_ether and enable generic eth port .Kindly advice.

    With Regards,

    Vasanth

  • 0 in reply to vasanth TP
    TI__Guru**** 170625 points

    Vasanth,

    vasanth TP said:
    Kindly let us know how to disable usb_ether and enable generic eth port .Kindly advice.

    Your subject is "AM335x DDR3 configuration". I do not see how your follow up questions are related to the subject. I would suggest you to open new e2e thread about your new questions. Make sense?

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    TI__Guru**** 393215 points
    Forum policy is one topic per thread, so seeing that your DDR is working now, this thread is considered answered and closed.