• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 101 subscribers
  • Views 1156 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5716: SYSBOOT15 functionality

Nathan Rabenold
Intellectual 745 points
Part Number: AM5716

Hi-

In reference to the technical reference manual:

  • Table 33-4 states, "sysboot[15] must be pulled to vdd for proper device operation (SR1.0).  Used to permanently disable the internal PU/PD resistors on pads gpmc_a[27:24, 22:19] (SR2.0)"
  • Section 5.3.3.1 has the following two notes:
    • "Upon boot time, sysboot15 set at '0' selects a DSP_CLK2 and a sysboot15 set at '1' selects a DSP_CLK3 divided clock version for the DSP subsystem logic and bus interfaces."
    • "Only DSP_CLK3 clock is supported on this SOC...for SR2.0 sysboot15 is configurable".

My questions are the following:

  1. What does syboot15 actually do?  Is is the PU/PD functionality or the DSP clock divider configuration?
  2. The second note referenced in Section 5.3.3.1 directly contradicts itself.  Can we or can we not use DSP_CLK3 configuration on an AM5716 device?

Thanks,

Nate

  • 0
    TI__Guru**** 393215 points
    Hi,

    I agree that this sounds confusing. However:

    1. SYSBOOT15 must be pulled to VDD on silicon revision 1.0 devices.
    2. On Silicon Revision 2.0 devices SYSBOOT15 controls the internal PU/PD resistors on pads GPMC_A[27:24, 22:19].
    3. Only DSP_CLK3 clock is used on these devices (both SR1.0 and 2.0). SYSBOOT15 cannot be used to change this to DSP_CLK2.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 745 points
    Biser-

    I know this is a while back, but could you please clarify one point in your response:

    "Only DSP_CLK3 clock is used on these devices (both SR1.0 and 2.0). SYSBOOT15 cannot be used to change this to DSP_CLK2."

    Are you saying that, in SR2.0, SYSBOOT15 does not affect the DSP_CLK setting, and therefore we can use it configure the GPMC PU/PD? Or are you saying that we cannot change SYSBOOT15 since it affects the DSP_CLK2 setting? If you meant the first option, then these statements from the TRM about SYSBOOT15 controlling the DSP_CLK setting are not true for SR2.0, correct?

    Thanks,
    Nate
  • 0 in reply to Nathan Rabenold
    TI__Guru**** 393215 points

    See the second note in section 5.3.3.1 of the TRM:

    "Only DSP_CLK3 clock is supported on this SoC. For proper device operation, sysboot14 must be tied to vss. For SR1.0, sysboot15 must be tied to VDD, but for SR2.0 it is configurable. For more information, see Section 18.4.6.1.1.1, Permanent PU/PD disabling (SR 2.0 only) in Chapter 18, Control Module."

  • 0 in reply to Biser Gatchev-XID
    Intellectual 745 points

    So the note directly above that one in the TRM is wrong for SR2.0?  I don't see how sysboot15 can both adhere to this statement as well as be configurable given what you highlighted above.

    "Upon boot time, sysboot15 set at '0' selects a DSP_CLK2 and a sysboot15 set at '1' selects a DSP_CLK3 divided clock version for the DSP subsystem logic and bus interfaces."

    Thanks,

    Nate

  • 0 in reply to Nathan Rabenold
    TI__Genius 15760 points

    Hi Nate,

    SYSBOOT15 has different functionality in SR1.0 and SR2.0.  

    In SR1.0, SYSBOOT15 selects the DSP_CLK.  Because only DSP_CLK3 is supported, SR1.0 requires that SYSBOOT15 be set at '1'.

    In SR2.0, SYSBOOT15 configures the GPMC_A[27:24, 22:19] pads internal PU/PD.  Therefore, it can be set to '0' or '1' depending on your PU/PD requirements.  Note on SR2.0, setting SYSBOOT15 to '0' has no impact on DSP_CLK.

    Regards,

    Melissa