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DRA746: When are pull-down resistors disabled by setting SYSBOOT15=1?

Manfred Becker
Expert 4570 points
Part Number: DRA746

A customer would like to know if setting SYSBOOT15=1 (SR 2.0) disables all MMC2 related pull-down resistors already during PORZ=0 or only after a PORZ reset release. He's concerned on getting undefined input voltages on the eMMC device if J6 pull-downs on these signals could still be enabled during an active power-on reset.  Can anybody clarify if SYSBOOT15=1 disables the pull-downs as soon as all supply voltages are valid or indeed just after the release of PORZ?


Best regards,

Manfred

  • 0
    TI__Genius 15120 points

    Hi Manfred,

    This is how sysboot[15] = 1 is described in TRM:

    "Internal pull-down resistors permanently disabled to avoid contention with the
    recommended per eMMC standard pull-ups that should be present on PCB. Software reconfiguration
    of internal pull resistors is disabled."

    This patch was done in SR2.0 due to incorrectly set pulldowns at POR. From erratum i863:

    "On SR2.x, if SYSBOOT15=1 then no software workaround is required since the internal
    pulls are permanently disabled. Note that external pull-up resistors on the MMC data bus
    are mandatory in this case. It is OK if the software workaround remains since accesses
    to configure the internal pulls has no effect."

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Genius 15120 points
    Since it is a hardware patch (not ROM update), most probably pulldowns are disabled since the beginning (as soon power ramps and during POR).
    Even if it wasn't so, I don't understand the concerns. During POR, eMMC is not clocked, no software accesses, and most probably eMMC is under reset...
  • 0 in reply to Stanislav Stilyanov
    TI__Expert 4570 points
    Thanks Stan,

    just from reading this description in the TRM it didn't become clear for us if these internal pull-down resistors are definitely disabled for the period between all supply voltages reaching a valid level and the final release of the PORZ signal. This could easily be a few ms while there may still be a contention between internal pull-down and external pull-up resistors if the J6 pull-downs are not already disabled. Therefore the customer wanted to get this clarified if possible.

    Best regards,
    Manfred
  • 0 in reply to Manfred Becker
    TI__Genius 15120 points
    Manfred,
    I agree, the description is not 100% clear.
    I'm curious why they are wishing to know that. The worst thing can happen is several hundreds of wasted microamperes flowing for just several milliseconds. That is, MMC function is unaffected, since there is no MMC transfers during that period (POR asserted).
    See also my previous post in case you missed it (I posted soon after my first one).
    If they still need confirmation, I can ask the team.

    Regards,
    Stan
  • 0 in reply to Stanislav Stilyanov
    TI__Expert 4570 points
    Stan,

    the combination of pull-up resistors for the eMMC CMD and DAT lines together with the J6 internal pull-down resistors for these signals could result in input voltages for the attached eMMC device which are close to the switching threshold. If the eMMC memory doesn't use input buffer with hysteresis, that may result in a significant cross-current through the input buffer's transistors (similar to the floating input problem described in the SCBA004D application report). The customers sees this as a reliability issue for the attached eMMC device.

    Regards,
    Manfred
  • 0 in reply to Manfred Becker
    TI__Genius 15120 points
    Pulldowns are disabled from power up.
    It is confirmed after internal discussion.