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TMS320C6657: Timing for EMIF nor flash interface, hold time constraint not met.

Part Number: TMS320C6657

I was performing timing analysis on the RC28F128P30B65 Nor flash and the TMS320C6657 using the EMIF interface.  To me it looks like this NOR does not work due to timing parameter denoted as R10 (Output hold from first occurring address, CE#, or OE# change)  min 0 nS in the data sheet.  Also see figure 26 in the data shee (Asynchronous Read-to-Write Timing).  This is because in the ti emif timing specifications th(OEH-D) (Input hold time from OE high to D invalid) is a minimum of 0.5 nS.  See table 5-17 EMIF16 Asynchronous Memory Timing Requirements and figure 5-20 below.

Is there any way around this besides using external parts?

 see this link for nor data sheet download:

 

  • Hi Paul,

    I've notified the design team. their feedback will be posted here.

    Best Regards,
    Yordan
  • Hi Paul,

    There isn't a way to program the EMIF interface to compensate for that 500ps hold time requirement on the data input. Most customers will use the delay associated with the PCB to achieve the hold requirement. Remember that the timing is measured at to the pins of the C6657. Once the OE signals is launched there is some delay between when the signal is valid at the pin of the C6657 and when the signal arrives at the memory component. There is additional delay for the data signals to return. As you increase the length of the OE and data lines, you increase the hold time on a read access. 

    Regards,

    Bill

  • Thank you,  as a side note the i ofund out the memory part is going obsolete.  Switching to a new memory now.