TMS320C6678: PIN conflict on C6678L EVM

Hi Murad,

I've forwarded this to the design team. Their feedback should be posted here.

BR
Tsvetolin Shulev

Murad,

Was your question answered here:
e2e.ti.com/.../564597

Or you still looking for guidance on enabling this functionality?

Regards,
Rahul

Not the same question.
I want to have ibl nor boot but also want to select the PA clock to be the core clock using BM_GPIO settings...this seems impossible?...can you verify please

Regards

Murad

Murad,

I think you are mis-interpreting the BOOTMODE pins in  data sheet and schematics. The PLL setting option only applies to boot modes other than SPI and I2C. The BootROM doesn`t configure the PLLs in I2C and SPI boot modes so the PLL settings table doesn`t apply to those boot modes.

To make my point clear, I have put together all the tables corresponding to BOOTMODE[12:0] in DEVSTAT from the datasheet. check for the interpretation of BOOTMODE[12:10], this directly corresponds to the way the GPIO pins are hooked up to the BMC.  For I2C boot the PLL setting pins are used to specify speed and address parameters.  For all other boot modes, those same pins are used to specify the PLL setting.

So the option to drive  PA using core clock is available only on boot modes other than SPI and I2C.

Regards,

Rahul

Thank you Rahul for the clarification.
So, I2c boot and IBL take care of the PLL settings.
My design doesn't have an external PA clk...does the I2c Nor boot assumes PA clock driven from core clk?
Please see my post
e2e.ti.com/.../564587

Regards,

Murad

Hi Murad,

To be clear, the PACLKSEL only determines the source of the clock input to the PA PLL. The I2C NOR boot configures the PLL based on the expected frequency of the input clock to the PA PLL. If you are selecting a different source for the PA PLL but the frequency is the same, no change to the software is needed. If the frequency is different, you will have to modify the PLL configuration code.

Regards,

Bill

Thank you Bill for the reply,
you wrote: "The I2C NOR boot configures the PLL based on the expected frequency of the input clock to the PA PLL."
How do I know the frequency used with I2C NOR boot?...our design is based on C6678 EVM with core clk= 100 MHz...is I2C NOR boot using core clk to drive the PA clk?...if that is the case, then we are ok...but if I2C NOR boot is using external PA clk, then we need to either supply an external PASS clk (Design change) or change the I2C NOR boot (trying to avoid)

Regards,

Murad

Thanks a lot Bill,
This is what I wanted to hear!...I even forced the PACLKSEL to 0 in the FPGA code of the C6678 EVM and everything worked fine!...I wasn't sure if the I2C NOR boot uses this signal or not...now I know :-)...Thanks again!

Regards,

Murad

Thanks a lot Bill,
This is what I wanted to hear!...I was able to force the PACLKSEL to low in the FPGA code of the EVM and everything worked fine!...I wasn't sure if the I2C NOR uses this signal or not...now I know :-)...Thanks again,

Regards,

Murad