I was thinking about using the EMIFA on a C6748 to configure an Altera Cyclone III FPGA in their "fast passive parallel" (FPP) mode. It seems like this should be possible by using a few GPIO lines to control the Altera config pins. The EMIFA could then read the configuration data file from an ansychronous flash device onto the bus and use either the EMA_CLK or another GPIO to clock the data into the Altera.
w.r.t the EMA_CLK I know that the EMA_CLK is not truly relevant in asynchronous mode, but since the clock is still externally available on the device and seems synchronous to the EMA_OE in either mode, I wonder if it is possible.
Additionally by setting the configuration Data pins as I/O, the FPGA could be used as a device on the EMIFA after configuration.
Has anyone tried this or something similar?