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AM3352: EMAC boot PHY address

Thomas Langhammer
Intellectual 580 points
Part Number: AM3352

Hi,

I am using an AM3352 device on a custom board. For production programming I would like to use EMAC1 boot.
TRM "26.1.8.4.1 Device Initialization" describes ethernet PHY addressing "In dual-port configurations, the ROM code assumes that the Ethernet PHY with the lowest MDIO address (0-31) is connected to CPGMAC port"
I do have dual port config and several (5) PHYs connected to AM3352 MDIO port (PHY addresses 1-5), and the PHY that connects to EMAC1 has address "5" (which is the one with the _highest_ address, not with the _lowest_).
From TRM description I would assume that I need an ethernet link at the lowest PHY address (here: 1) in order to get EMAC1 boot working. However EMAC1 booting works when I have an ethernet link at PHY address 5 and without ethernet links on PHY addresses 1-4
Is this an issue of the TRM description or of the boot code inside the AM3352?
The behaviour is perfect for my setup, but I need to be sure that this is not an unexpected deviation from boot code that will be fixed sometimes, breaking my production setup.

Regards

tom

  • 0
    TI__Guru**** 393215 points
    Hi,

    From the same TRM section:

    Device detects if the PHY is alive on the MDIO interface and:
    – Reads the STATUS register to check if Ethernet link is active
    – Reads the CONTROL register to detect the auto-negotiated mode of operation
  • 0 in reply to Biser Gatchev-XID
    Intellectual 580 points
    Hi,

    I am aware that the AM3352 detects whether the PHY is alive and checks the link status.
    My concern is about the PHY MDIO address, i.e. which PHY is checked whether it is alive and the link status of which PHY is queried if more than one PHY is connected to MDIO bus.
    TRM says that only the PHY with the lowest MDIO address is used, but I can see that the PHY with the highest MDIO address is used.

    Best Regards
    Tom
  • 0 in reply to Thomas Langhammer
    TI__Guru**** 393215 points
    How are the other PHY's connected in your design? Can you see MDIO poll all of them?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 580 points
    All 5 PHYs are connected in parallel to the AM3352 MDIO bus and set up to different MDIO addresses (1-5).
    I can poll all of them as expected, and I can verify the correct assignment of the 5 different MDIO addresses when linux is running.
    When AM3352 starts EMAC1 boot I can see the polling of the PHYs on MDIO bus with an oscilloscope (however I need to manually read the bits and put it all together), and I can see that the PHYs with MDIO adresses 1-5 are responding.
    However when I inspect the register values returned via MDIO, I can see PHYs with MDIO addresses 1-4 are returning 0x3808 for Register 1 (which means "no link") and PHY with MDIO address 5 is returning 0x382c (link detected).
    From TRM point of view I would assume AM3352 is evaluating the PHY with the lowest MDIO address (=1), but this one returns "no link". It looks like AM3352 evaluates the PHY with address 5 instead, because it generates bootp frames according to the settings of this PHY.

    Best Regards
    Tom
  • 0 in reply to Thomas Langhammer
    TI__Guru**** 393215 points
    Thomas Langhammer said:
    However when I inspect the register values returned via MDIO, I can see PHYs with MDIO addresses 1-4 are returning 0x3808 for Register 1 (which means "no link") and PHY with MDIO address 5 is returning 0x382c (link detected).


    That's it. This is the only PHY that is linked to the network.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 580 points
    Yes, the only PHY that is linked to the network is PHY with MDIO address "5".
    But TRM says at 26.1.8.4.1 "In dual-port configurations, the ROM code assumes that the Ethernet PHY with the lowest MDIO
    address (0-31) is connected to CPGMAC port 1"
    So this means to me ROM code assumes the PHY with the lowest MDIO address (here: 1, from addresses 1-5 present) is connected to CPGMAC Port 1.
    But I have connected PHY with the highest address (here: 5) to CPGMAC port 1, and ROM code scans link availability for this MDIO address (5) instead of the lowest one (1).
    So it looks like the measured behaviour does not match the TRM description.
    Regards
    Tom
  • 0 in reply to Thomas Langhammer
    TI__Guru* 80020 points

    Hi Tom,

    to clarify what the ROM is doing, it does cycle through the PHY addresses starting from address 0.  With each address, it is specifically looking for link status in each of the PHYs (in MII_STATUS_REG).  In your case, since link status fails with PHY addresses 1-4, it settles on PHY addr 5 since it read a active link state from that PHY, and starts sending BOOTP packets to that address.  Does that clear it up?  If so, i can add some wording to the TRM.

    Regards,

    James

  • 0 in reply to JJD
    TI__Guru* 80020 points

    Hi Tom, I'm curious to know how you have the 5 PHYs connected in your design?  Which MACs are they connect to, or do you have a switch in between?

    More clarification on my last sentence:  In your case, since link status fails with PHY addresses 1-4, it settles on PHY addr 5 since it read a active link state from that PHY, and thus the ROM assumes PHY addr 5 is connected to EMAC1 port and starts sending BOOTP packets to that port.  If a link is active on PHYs 1-4 during boot, the ROM will assume that PHYs is connected to EMAC1 (the first one it encounters with active link starting from PHY addr 0), and start sending BOOTP packets to EMAC1 port.

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 580 points
    Hi James,

    with your description everything is clear now, so I can be sure my design is safe for production. Thank you!
    TRM clarification could help, but maybe I am the only one that understood it this way.
    Regarding your question about the 5 PHYs: I have a 5 port switch with integrated PHYs (Micrel KSZ8895) attached to the AM3352. This switch has one separated PHY which I connect to EMAC1 via MII. The switch with the 4 PHYs has a second MII port which I connect to EMAC2.
    The PHY addresses are fixed inside the chip, so I have MDIO address 5 set for the single PHY attached to the EMAC1 port (the one that I want to use for BOOTP). The other 4 ports are disabled by power up default so I only can use port 5 for BOOTP.

    Best Regards
    Tom