Hi,
We are working on interfacing SRIO communication between FPGA and Keystone 2 Processor.
Config Details
Link Speed - 5Gbps per port,
Port Mode - 4X
NWrite packet
In our setup, the FPGA GTX Transreceivers are directly connected to the DSP SRIO Serdes lanes.
The SRIO code is initialized on the DSP core 0 of the Keystone 2 Processor.
Issue:
We are facing some issue while transferring data from FPGA to DSP. The DSP able to receive approximately 16MB of data from FPGA then it enter into Input Retry Stopped Error.
The Input Retry Stopped Error Bit keeps on Toggling on the DSP side.
The packet formation on the FPGA side also stopped due to packet stop at retry state request from DSP.
Similarly when we tested the same FPGA with Keystone 1 processor, data transferring working without any issue.
We tested the below scenarios where data transferring from FPGA to DSP working without any issue.
|
S.No |
Setup Type |
Status |
Error |
|
1 |
FPGA to Keystone 1 (Direct Connection ) |
Working |
Continuous Streaming of Data |
|
2 |
Keystone 2 to Keystone 2 (Direct Connection ) |
Working |
Continuous Streaming of Data |
|
3 |
FPGA (EVM setup ) to Keystone 2 |
Working |
Continuous Streaming of Data |
What is the difference in running SRIO on Keystone 1 and Keystone 2 ?
Please provide us the solution to solve this issue .
Thanks and Regards,
Narayan
