Other Parts Discussed in Thread: TPS54160
To Whom Has the Answer
I have designed a custom TMS320DM6437ZWT400 V1.3 board for video surveillance. Of a batch of 100 populated boards about 75% fail setup of the PLL1.
I will describe the setup of the hardware before describing the error, after which I will describe an attempt at a solution and lastly the error message will be shown.
Note: The code was modified from development kit code and is attached.
Hardware Description:
The voltages supplied to the DSP is regulated by three TI TPS54160 SMPS with sequencing and meets requirements on an oscilloscope. A voltage of 1.2V is used instead of 1.05V
A 27MHz crystal is used with 22pF capacitors that are connected to MXvss via a 0Ohm resistor, with MXvdd connected to 1.8V via a 0Ohm resistor.
The PLL power is derived from the 1.8V supply and passed through a ferrite (Murata BLM21PG221SN1D) and then bypassed by a 1uF, 100nF and 1nF before being sent to ball L16 (ZWT).
EMU0 and EMU1 are left floating (little documentation on these balls have been found) but both balls can be pulled high or low. Any link to documentation would be appreciated.
The reset (M4, ZWT) ball is ‘pulled’ high via a 10kOhm resistor. A 1uF capacitor is connected between reset and ground.
The emulator header (14 way keyed) is directly connected to the emulator balls of the DSP. Only EMU0 and EMU0 have extra components connected for potentially connecting ‘pull up’ and ‘pull down’ resistors.
Ball H16 (ZWT) has a 10kOhm resistor to ground, and ball H17 (ZWT) has a 10kOhm resistor to +3.3V.
The fastboot, bootmode0 and bootmode1 balls are connected directly to ground. The bootmode 2 ball is connected to +3.3V via a 0Ohm resistor, but can be connected to ground. The bootmode 3 ball is connected to ground via a 22kOhm resistor, but can be connected to +3.3V. The AEM0 and AEAW2 balls are connected to +3.3V via 22kOhm resistors. The AEM1, AEM2, AEAW0 and AEAW1 balls are connected to ground via 22kOhm resistors. CS2 and CS4 are ‘pulled’ high by 22kOhm resistors. This is setup for bypass flash boot, but is not used at present until debug is complete. Will having bypass flash boot effect emulation boot at all? Connection using the emulator is achieved despite this setting.
Problem Description:
A modified GEL file was used to connect and setup the custom DSP board. Upon attempting to setup the PLL1, which supplies the clocking for the DSP core, the DSP would lock up and further attempts to connect to the DSP via the emulator would result in errors, see Error 01 below. This is the PLL Multiply Control Register, which is checked after the PLL is setup to indicate the core frequency via the debug output, at line 117 of GEL_SETUPPLL1 in the attached file. Emulation loss is confirmed at line 115 of GEL_SETUPPLL1 in the attached file, and an external reset or power cycle is required for emulator reconnection.
Solution Attempt:
A workaround has been found, but this workaround only create more questions.
Firstly the setup of the PLL1 and PLL2 is removed from the GEL file; the removal of lines 8 to 11 in GEL_ONTARGETCONNECT in the attached file.
After connecting to the unit with this modified GEL file a program is loaded. This program is run and if the LEDs on the custom board light up and the word “FINE” is output on the serial port setup of the PLL1 is successful. The source code loaded on the DSP is shown in the attached file.
Error 01:
Trouble Reading Memory Block at 0x1c40910 on Page 0 of Length 0x4:
Error 0x00000002/-1139
Error during: Memory,
Device driver: Emulation Connection Loss Detected on Target CPU.
It is recommended to RESET EMULATOR. This will disconnect each
target from the emulator. The targets should then be power cycled
or hard reset followed by an emureset and reconnect to each target.
Sequence ID: 69
Error Code: -1139
Error Class: 0x00000002
I would really really like a solution to and explanation of this error.
Thank you
Francois
