Tool/software: Linux
when i use DVRRDK4.0 package, the link is cap-enc, 2 chn, 8 bit,only use vip0. if fpga send the same head, cap is ok, if fpga send different head, cap error, print"CAPTURE: Overflow detected pnVIP0, Total Reset = …". now, i don't know how to solve it. can you help me.thx