TMS320C6657: DDR3 controller timings

paul kerstetter

Part Number: TMS320C6657

I'm setting up a timing model in the ddr wizard in hyperlynx and it asks for timing information for theDDR3 controller. Where is this information. I have looked in the three available DDR3 documents and the data sheet. Maybe I missed I. One specific question (the most important one) is: Is 2T or T timing used wit this controller. Address/Command time valid before CK rising edge (earliest and latest), DQS rising edge with respect ot CK edge (earliest an latest), DQ/DM transition window before DQS transitions (earliest and latest), DQ Setup/Hold/Phase shift.

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,

See Section 5.7.7 DDR3 Memory Controller Electrical Data/Timing from TMS320C6657 Data Manaul and KeyStone DSP DDR3 Implementation Guidelines (www.ti.com/.../sprabi1b.pdf).

Best Regards,
Yordan

0 paul kerstetter over 8 years ago in reply to Yordan Kovachev

Intellectual 455 points

Im pretty sure those two documents do not have the information I need. Although i do see an interesting section on limitation of max min skew between command delay and data delay....

0 paul kerstetter over 8 years ago in reply to paul kerstetter

Intellectual 455 points

/****************************************************************************************
* HyperLynx DDR3 Controller Timing Model Parameters
*
* A controller timing model should define the following parameters:
*
* All cycles:
* tACCSkew Output delay skew from CK falling to Addr/Cmd/Ctl (+/-)
*
* Write cycles:
* tCKDQS Output delay skew from CK rising to DQS rising (+/-)
* tDQSDQQ Output delay skew from DQS to DQ (+/-)
*
* Read cycles
* tDS Minimum DQ to DQS setup time, with 1/4 cycle DQS shift
* tDH Minimum DQS to DQ hold time, with 1/4 cycle DQS shift
*
****************************************************************************************/

0 Tom Johnson 16214 over 8 years ago in reply to paul kerstetter

TI__Mastermind 46460 points

Paul,

That information is not available. Please refer to DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B). TI has qualified SDRAM topologies for customer implementation. Timing analysis was performed to validate that the supported topologies will meet timing with our KeyStone devices. Customers need to follow the guidelines in the referenced document including the length matching rules and the requirements for proper track spacing and reference planes. This will guarantee that you have a robust system.

Tom

0 paul kerstetter over 8 years ago in reply to Tom Johnson 16214

Intellectual 455 points

Can you at least tell me if it is 1T or 2T timing? in other words the address signal transitions with a valid address every clock rising edge 1T or transitions every other rising edge with valid address information 2T? I really wish this information was available. The simulator simulates process variations and helps identify termination settings in the ddr3. Customer implementations are not always ideal. Certainly TIs controller does work, but then it is implemented on a PCB board by the customer. No two PCB boards are alike. No two implementations are the same. The simulator helps improve the implementation done by the customer and helps verify the implementation is correct. If it finds and error it saves an enormous amount of time debugging in the lab. This is the modern way of doing things. TI needs catch up to the times and support these methods of proving out a design.

0 Senthilkumar Srinivasan over 8 years ago in reply to paul kerstetter

TI__Mastermind 43660 points

Paul,

I got some information for regarding 1T/2T timing. All our testing was performed with 1T command rates and 2T command rate is not supported in KeyStone I or KeyStone II devices.

e2e.ti.com/.../329081

Regards,
Senthil

0 Tohar Cohen over 8 years ago in reply to paul kerstetter

Prodigy 30 points

I completely agree with Paul.
Each design has its requirements and trade-offs, it's impossible to follow the the design guidelines in 100%.
I hope you'll work on this soon, since this is what customers need these days (including me).

0 Tom Johnson 16214 over 8 years ago in reply to Tohar Cohen

TI__Mastermind 46460 points

Tohar,

We do not agree. Robust simulation requires significant experience and understanding. It is very easy to set up simulations that provide false indications of success. Through our experiences with many customers, we have determined that the best path to success is to only support a limited number of topologies and to provide rules related to impedances, lengths and PCB constructs. We expect customers implementing DDR layouts to follow 100% of the routing rules given. Customers that do not follow all of the rules provided routinely have unstable DDR implementations. Customers the understand and follow the rules provided have robust designs.

Tom

0 Tohar Cohen over 8 years ago in reply to Tom Johnson 16214

Prodigy 30 points

Hi Tom,

Thanks for taking the time to respond.

My intention wasn't to suggest to ignore the PCB guidelines. I fully understand that these guidelines were written after massive simulations and measurements., and best thing to do is follow the guidelines.

but, in my expirience, you can't follow the guidelines in 100%.

i've met requirements like -

* routing each ACC signal in one layer from controller to last DRAM, in a 5 DRAM DDR4 interface

* limiting the traces length in DRAM breakout to 100 mils (DQ)

* instructing to route DDR interface in upper layers (3,5)

if you're limited in the number of layers you assign to DDR interface, and limited in PCB area (DRAMs are very close to the controller) - the guidelines i showed above can't be 100% followed (and this is just an example).

this is where simulations come in.

you can verify that your design is still robust, even when some of the guidelines are not followed, due to design constraints.

i'll appriciate your response.

Thanks,

Tohar

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TMS320C6657: DDR3 controller timings