Hi,
Questions about AM3358BZCZ100 GPMC bus timing.
The attached figure shows the waveform of GPMC connected to spartan 6 and observed with Chipscope and circuit diagram.
GPMC's GPMC_FCLK(bus) frequency is 104 MHz, but within Spartan 6 it is synchronized with a clock with a frequency of 105 MHz and it is used.
The sampling clock of Chipscope is 105 MHz.(105MHz = 24MHz(clkout) x 4.375 Spartan 6 inner PLL )
The following is a question.
The rising edge of we_d <1> is 4 cycles after the rising edge of cs_d <1>, but in theory it should be 2 or 3 cycles.
(we_d <1>,cs_d <1>,oe_d <1> is positive logic.)
1cycle vary from sampling timming , why 2cycles over ?
cpu bus issue?
I want to know the reason why such things happen.
GPMC bus timing settings are as follows.
R/W async,single mode , 16bits data bus , adr/data mux
//----------------------------------------
// FPGA sp6 bus settings
//----------------------------------------
FCLKDIVIDER 0
CSWROFFTIME 10
CSRDOFFTIME 10
CSEXTRADELAY 0
CSONTIME 1
ADVAADMUXWROFFTIME 0
ADVAADMUXRDOFFTIME 0
ADVWROFFTIME 2
ADVRDOFFTIME 2
ADVEXTRADELAY 0
ADVAADMUXONTIME 0
ADVONTIME 1
WEOFFTIME 9
WEEXTRADELAY 0
WEONTIME 3
OEAADMUXOFFTIME 0
OEOFFTIME 10
OEEXTRADELAY 0
OEAADMUXONTIME 0
OEONTIME 3
PAGEBURSTACCESSTIME 0
RDACCESSTIME 9
WRACCESSTIME 9
WRCYCLETIME 11
RDCYCLETIME 11
WRDATAONADMUXBUS 3
CYCLE2CYCLEDELAY 1
CYCLE2CYCLESAMECSEN 0
CYCLE2CYCLEDIFFCSEN 0
BUSTURNAROUND 1
IOREG32( GPMC0_BASE, GPMC_CONFIG1(1) ) = 0x1200 | FCLKDIVIDER | (1<<22) | (1<<21) | (1<<18) ; // R(b21)/W(b22) wait monitor
IOREG32( GPMC0_BASE, GPMC_CONFIG2(1) ) = ( CSWROFFTIME << 16 ) | ( CSRDOFFTIME << 8 ) | ( CSEXTRADELAY << 7 ) | CSONTIME;
IOREG32( GPMC0_BASE, GPMC_CONFIG3(1) ) = ( ADVAADMUXWROFFTIME << 28 ) | ( ADVAADMUXRDOFFTIME << 24 ) | ( ADVWROFFTIME << 16 ) | ( ADVRDOFFTIME << 8 )
| ( ADVEXTRADELAY << 7 ) | ( ADVAADMUXONTIME << 4 ) | ( ADVONTIME );
IOREG32( GPMC0_BASE, GPMC_CONFIG4(1) ) = ( WEOFFTIME << 24 ) | ( WEEXTRADELAY << 23 ) | ( WEONTIME << 16 )
| ( OEAADMUXOFFTIME << 13 ) | ( OEOFFTIME << 8 ) | ( OEEXTRADELAY << 7 ) | ( OEAADMUXONTIME << 4 ) | OEONTIME ;
IOREG32( GPMC0_BASE, GPMC_CONFIG5(1) ) = ( PAGEBURSTACCESSTIME << 24 ) | ( RDACCESSTIME << 16 ) | ( WRCYCLETIME << 8 ) | RDCYCLETIME;
IOREG32( GPMC0_BASE, GPMC_CONFIG6(1) ) = ( WRACCESSTIME << 24 ) | ( WRDATAONADMUXBUS << 16 ) | ( CYCLE2CYCLEDELAY << 8 )
| ( CYCLE2CYCLESAMECSEN << 7 ) | ( CYCLE2CYCLEDIFFCSEN << 6 ) | BUSTURNAROUND;
IOREG32( GPMC0_BASE, GPMC_CONFIG7(1) ) = 0xf00| 0x0040 | 0x18; /* CSn(1) addr.= 0x18000000 FPGA*/
//
// ---------------------------------
//
Regards,
Isao
