U-Boot/AM572x: DSS/DISPC driver

jinhu wu

Intellectual 800 points

Other Parts Discussed in Thread: SYSCONFIG, DM3730

Hi, all

I want to display some splash screen on uboot.

but can not found any simple driver of DSS/DISPC for am572x in SDK

Is there any support?

I also try setting register according to CPU Manual and register value dumped from linux

All I want is to make a simple dss/dispc driver. Only output to LCD1(DPI1).

Table below is the comparation of register setting between Linux and U-Boot.

Item
		DSS(Linux)	DSS(U-Boot)
1	DSS_REVISION	00000061	00000061
2	DSS_SYSCONFIG	00000000	00000000
3	DSS_SYSSTATUS	00000001	00000001
4	DSS_CONTROL	00010001	00010000
5	DSS_STATUS	01408a82	01408a81
6	PM_DSS_PWRSTCTRL	00030000	00030000
7	PM_DSS_PWRSTST	00000037	00000037
8	PM_DSS_DSS_WKDEP	00000000	00000000
9	RM_DSS_DSS_CONTEXT	00000000	00000103
10	PM_DSS_DSS2_WKDEP	00000000	00000000
11	RM_DSS_BB2D_CONTEXT	00000101	00000101
12	RM_DSS_SDVENC_CONTEXT	00000001	00000001
13	CM_DIV_H12_DPLL_PER	00000204	00000204
14	CTRL_CORE_CONTROL_IO_2	00000001	00000001
15	CM_DSS_CLKSTCTRL	00000703	00000203
16	CM_DSS_DSS_CLKCTRL	00001102	00060102
17	CTRL_CORE_DSS_PLL_CONTROL	000002a6	000002af
		DISPC(Linux)	DISPC(U-Boot)
18	CTRL_CORE_SMA_SW_1	00410000	00410000
19	DISPC_REVISION	00000051	00000051
20	DISPC_SYSCONFIG	00002015	00002015
21	DISPC_SYSSTATUS	00000001	00000001
22	DISPC_IRQSTATUS	00000020	000102a2
23	DISPC_IRQENABLE	1694564e	00000000
24	DISPC_CONTROL	00018309	00018309
25	DISPC_CONFIG	0000020c	0000020c
26	DISPC_CAPABLE	00000000	00000000
27	DISPC_LINE_STATUS	00000150	0000003c
28	DISPC_LINE_NUMBER	00000000	00000000
29	DISPC_DIVISOR	00010001	00010000
30	DISPC_GLOBAL_ALPHA	ffffffff	ffffffff
31	DISPC_GLOBAL_MFLAG_ATTRIBUTE	00000001	00000001
32	DISPC_DEFAULT_COLOR(LCD)	00000000	00000000
33	DISPC_TRANS_COLOR(LCD)	00000000	00000000
34	DISPC_SIZE_MGR(LCD)	0257031f	0257031f
35	DISPC_TIMING_H(LCD)	0570277f	0570277f
36	DISPC_TIMING_V(LCD)	01700103	01700103
37	DISPC_POL_FREQ(LCD)	00073000	00073000
38	DISPC_DIVISORo(LCD)	00010004	00010005
39	DISPC_DATA_CYCLE1(LCD)	00000000	00000000
40	DISPC_DATA_CYCLE2(LCD)	00000000	00000000
41	DISPC_DATA_CYCLE3(LCD)	00000000	00000000
42	DISPC_CPR_COEF_R(LCD)	00000000	00000000
43	DISPC_CPR_COEF_G(LCD)	00000000	00000000
44	DISPC_CPR_COEF_B(LCD)	00000000	00000000
45	DISPC_OVL_BA0(GFX)	7fda8000	7fda8000
46	DISPC_OVL_BA1(GFX)	7fda8000	7fda8000
47	DISPC_OVL_POSITION(GFX)	00000000	00000000
48	DISPC_OVL_SIZE(GFX)	0257031f	0257031f
49	DISPC_OVL_ATTRIBUTES(GFX)	020040b1	020040b1
50	DISPC_OVL_FIFO_THRESHOLD(GFX)	07ff07f8	07ff07f8
51	DISPC_OVL_FIFO_SIZE_STATUS(GFX)	00000500	00000500
52	DISPC_OVL_ROW_INC(GFX)	00000381	00000381
53	DISPC_OVL_PIXEL_INC(GFX)	00000001	00000001
54	DISPC_OVL_PRELOAD(GFX)	000007ff	000007ff
55	DISPC_OVL_MFLAG_THRESHOLD(GFX)	05000400	05000400
56	DISPC_OVL_WINDOW_SKIP(GFX)	00000000	00000000
57	DISPC_OVL_TABLE_BA(GFX)	00000000	00000000

Problem:

1.My clock path: DSS_GFCLK->DSS_CLK->LCD1_CLK->PIXEL_CLK. Is that right?

2.My module path: DSS->GFX->LCD1, Is that right?

3.After setting, I can measure the pixel clock and frame rate from pin, but there is nothing display on screen, event though I change some pixel value accoring to gfx base 7fda8000.

4.From CPU manual, the DMA of DISPC is no need to set, using default is ok. Right?

5.I miss some register?

Can you give me some suggestion to solved the problem?

Or Can you give me some suggestion to let me know how to debug the DSS/DISPC on U-Boot.

over 8 years ago

0 jinhu wu over 8 years ago

Intellectual 800 points

anybody can help me?

0 Steve Kipisz over 8 years ago in reply to jinhu wu

TI__Genius 15510 points

I'm not that familiar with DSS/DISPC yet, but there is an OMAP3 DSS driver in u-boot. I don't know how similar OMAP3 DSS and AM572x DSS are. Take a look at drivers/video/omap3_dss.c and see if it helps.

Steve K.

0 jinhu wu over 8 years ago in reply to Steve Kipisz

Intellectual 800 points

I have been known that omap3_dss.c file.
And before the am572x project. I do some job about dm3730, which base on OMAP3 DSS, and success configing the DSS core.
But I think the am57xx DSS is more complicate than OMAP3 DSS.

The important point is I have no idea to debug the DSS on am572x.
Becasuse the signal is measured from pin, but nothing display. I think it maybe the gfx ba or dma.
From CPU manual, the dma seem auto, and nothing need to change.
How I can debug the dma transfer of dispc of DSS on U-boot?

0 jinhu wu over 8 years ago in reply to jinhu wu

Intellectual 800 points

I finally find out the problem.

The DMM/TILER module is need by DISPC DMA for image address mapping.

so I use DMM Direct Mapping . And the image is show.

But there is another problem:

The color display on screen is wrong, and not corresponding to the DISPC setting.

See picture below, the backgroup I set is 0, but the color on screen is cyan.

and color bar at top left I set is a gray scale(0-255), but the colors on screen are misc.

Is there any setting wrong? What I shoule check？

0 Steve Kipisz over 8 years ago in reply to jinhu wu

TI__Genius 15510 points

Can you post your code?

Steve K.

0 jinhu wu over 8 years ago in reply to Steve Kipisz

Intellectual 800 points

Fullscreen omap5_dss.c Download

#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>

#define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
#define FLD_MOD(orig, val, start, end) \
	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))


#define CM_DIV_H12_DPLL_PER     0x4A00815C

#define CTRL_CORE_CONTROL_IO_2  0x4A002558 
//DSS_DESHDCP_CLKEN 0 1

#define CM_DSS_CLKSTCTRL        0x4A009100
//CLKTRCTRL 0-1 2

#define CM_DSS_STATICDEP        0x4A009104
#define CM_DSS_DYNAMICDEP       0x4A009108

#define CM_DSS_DSS_CLKCTRL      0x4A009120
//OPTFCLKEN_DSSCLK 8 1
//MODULEMODE 0-1 2
//IDLEST 16-17 0

#define PM_DSS_PWRSTCTRL        0x4AE07100
//POWERSTATE 0-1 3

#define PM_DSS_PWRSTST          0x4AE07104
#define PM_DSS_DSS_WKDEP        0x4AE07120
#define RM_DSS_DSS_CONTEXT      0x4AE07124
#define PM_DSS_DSS2_WKDEP       0x4AE07128
#define RM_DSS_BB2D_CONTEXT     0x4AE07134
#define RM_DSS_SDVENC_CONTEXT   0x4AE0713C

#define CTRL_CORE_SMA_SW_1          0x4A002534
#define CTRL_CORE_DSS_PLL_CONTROL   0x4A002538 

#define DSS_BASE                0x58000000

#define DSS_REVISION			(0x0000)
#define DSS_SYSCONFIG			(0x0010)
#define DSS_SYSSTATUS			(0x0014)
#define DSS_CONTROL			    (0x0040)
#define DSS_STATUS			    (0x005C)

#define DSS_REG_GET(idx, start, end) \
	FLD_GET(dss_read_reg(idx), start, end)

#define DSS_REG_FLD_MOD(idx, val, start, end) \
	dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))

static inline void dss_write_reg(const u32 idx, u32 val)
{
	__raw_writel(val, DSS_BASE + idx);
}

static inline u32 dss_read_reg(const u32 idx)
{
	return __raw_readl(DSS_BASE + idx);
}

#define COM_REG_FLD_MOD(idx, val, start, end) \
	__raw_writel(FLD_MOD(__raw_readl(idx), val, start, end), idx)
#define COM_REG_GET(idx, start, end) \
	FLD_GET(__raw_readl(idx), start, end)

#if 1
#define DO_WAIT_OK          0
#define DO_WAIT_TIMEOUT     -1
static int do_wait(u32 reg,
                   u32 start,
                   u32 end,
                   u32 val,
                   u32 timeout_ms)
{
	ulong tm_start = get_timer(0);
    bool ok = false;

	while (get_timer(tm_start) < timeout_ms)
    {    
        printf("reg:%x = %x\n", reg, __raw_readl(reg));
        if (COM_REG_GET(reg, start, end) == val)
        {
            ok = true;
            break;
        }
        
    }

    if (ok == true)
    {
	    return DO_WAIT_OK;
    }
    else
    {
	    return DO_WAIT_TIMEOUT;
    }
}
#endif

/* DSS HW IP initialisation */
#define DSS_DUMPREG(r) printf("%-35s %08x\n", #r, dss_read_reg(r))
#define COM_DUMPREG(r) printf("%-35s %08x\n", #r, __raw_readl(r))

static int board_init_dss(void)
{
	u32 rev = 0;

	printf("%s, begin\n", __func__);

#if 0
    COM_DUMPREG(PM_DSS_PWRSTCTRL);
    COM_DUMPREG(PM_DSS_PWRSTST);
    COM_DUMPREG(PM_DSS_DSS_WKDEP);
    COM_DUMPREG(RM_DSS_DSS_CONTEXT);
    COM_DUMPREG(PM_DSS_DSS2_WKDEP);
    COM_DUMPREG(RM_DSS_BB2D_CONTEXT);
    COM_DUMPREG(RM_DSS_SDVENC_CONTEXT);

    COM_DUMPREG(CM_DIV_H12_DPLL_PER);
	COM_DUMPREG(CTRL_CORE_CONTROL_IO_2);
	COM_DUMPREG(CM_DSS_CLKSTCTRL);
	COM_DUMPREG(CM_DSS_DSS_CLKCTRL);

    DSS_DUMPREG(DSS_SYSSTATUS);
	DSS_DUMPREG(DSS_CONTROL);
	DSS_DUMPREG(DSS_STATUS);
#endif
    enable_dss_clocks();

    printf("enable_dss_clocks ok.\n\n"); 

    dss_write_reg(DSS_CONTROL, 0x00010000);

    printf("Select LCD1 channel output ok.\n\n"); 

    rev = dss_read_reg(DSS_REVISION);
	printf("OMAP DSS rev %d.%d\n",
			FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));

#if 0
    COM_DUMPREG(PM_DSS_PWRSTCTRL);
    COM_DUMPREG(PM_DSS_PWRSTST);
    COM_DUMPREG(PM_DSS_DSS_WKDEP);
    COM_DUMPREG(RM_DSS_DSS_CONTEXT);
    COM_DUMPREG(PM_DSS_DSS2_WKDEP);
    COM_DUMPREG(RM_DSS_BB2D_CONTEXT);
    COM_DUMPREG(RM_DSS_SDVENC_CONTEXT);

    COM_DUMPREG(CM_DIV_H12_DPLL_PER);
	COM_DUMPREG(CTRL_CORE_CONTROL_IO_2);
	COM_DUMPREG(CM_DSS_CLKSTCTRL);
	COM_DUMPREG(CM_DSS_DSS_CLKCTRL);
//	COM_DUMPREG(CTRL_CORE_DSS_PLL_CONTROL);

    DSS_DUMPREG(DSS_SYSSTATUS);
	DSS_DUMPREG(DSS_CONTROL);
	DSS_DUMPREG(DSS_STATUS);
#endif
	printf("%s, end\n", __func__);
	return 0;
}


/* DISPC common registers */
#define DISPC_BASE              0x58001000

#define DISPC_REVISION			0x0000
#define DISPC_SYSCONFIG			0x0010
#define DISPC_SYSSTATUS			0x0014
#define DISPC_IRQSTATUS			0x0018
#define DISPC_IRQENABLE			0x001C
#define DISPC_CONTROL			0x0040
#define DISPC_CONFIG			0x0044
#define DISPC_CAPABLE			0x0048
#define DISPC_LINE_STATUS		0x005C
#define DISPC_LINE_NUMBER		0x0060
#define DISPC_GLOBAL_ALPHA		0x0074
#define DISPC_GLOBAL_MFLAG_ATTRIBUTE	0x085C

#define DISPC_DEFAULT_COLOR     0x004C
#define DISPC_TRANS_COLOR       0x0054
#define DISPC_SIZE_MGR          0x007C
#define DISPC_TIMING_H          0x0064
#define DISPC_TIMING_V          0x0068
#define DISPC_POL_FREQ          0x006C
#define DISPC_DIVISORo          0x0070
#define DISPC_DIVISOR			0x0804

#define DISPC_DATA_CYCLE1       0x01D4
#define DISPC_DATA_CYCLE2       0x01D8
#define DISPC_DATA_CYCLE3       0x01DC

#define DISPC_CPR_COEF_R        0x0220
#define DISPC_CPR_COEF_G        0x0224
#define DISPC_CPR_COEF_B        0x0228

#define DISPC_OVL_BASE              0x0080
#define DISPC_BA0_OFFSET            0x0000
#define DISPC_BA1_OFFSET            0x0004
#define DISPC_POS_OFFSET            0x0008
#define DISPC_SIZE_OFFSET           0x000C
#define DISPC_ATTR_OFFSET           0x0020
#define DISPC_FIFO_THRESH_OFFSET    0x0024
#define DISPC_FIFO_SIZE_STATUS_OFFSET   0x0028
#define DISPC_ROW_INC_OFFSET 		0x002C
#define DISPC_PIX_INC_OFFSET        0x0030
#define DISPC_PRELOAD_OFFSET        0x01AC
#define DISPC_MFLAG_THRESHOLD_OFFSET 0x0860
#define DISPC_WINDOW_SKIP_OFFSET    0x0034
#define DISPC_TABLE_BA_OFFSET       0x0038

#define DISPC_OVL_BA0	            (DISPC_OVL_BASE + DISPC_BA0_OFFSET)
#define DISPC_OVL_BA1	            (DISPC_OVL_BASE + DISPC_BA1_OFFSET)
#define DISPC_OVL_POSITION	        (DISPC_OVL_BASE + DISPC_POS_OFFSET)
#define DISPC_OVL_SIZE		        (DISPC_OVL_BASE + DISPC_SIZE_OFFSET)
#define DISPC_OVL_ATTRIBUTES	    (DISPC_OVL_BASE + DISPC_ATTR_OFFSET)
#define DISPC_OVL_FIFO_THRESHOLD	(DISPC_OVL_BASE + DISPC_FIFO_THRESH_OFFSET)
#define DISPC_OVL_FIFO_SIZE_STATUS	(DISPC_OVL_BASE + DISPC_FIFO_SIZE_STATUS_OFFSET)
#define DISPC_OVL_ROW_INC		    (DISPC_OVL_BASE + DISPC_ROW_INC_OFFSET)
#define DISPC_OVL_PIXEL_INC		    (DISPC_OVL_BASE + DISPC_PIX_INC_OFFSET)
#define DISPC_OVL_PRELOAD		    (DISPC_OVL_BASE + DISPC_PRELOAD_OFFSET)
#define DISPC_OVL_MFLAG_THRESHOLD	DISPC_MFLAG_THRESHOLD_OFFSET
#define DISPC_OVL_WINDOW_SKIP	    (DISPC_OVL_BASE + DISPC_WINDOW_SKIP_OFFSET)
#define DISPC_OVL_TABLE_BA		    (DISPC_OVL_BASE + DISPC_TABLE_BA_OFFSET)

#define DISPC_REG_GET(idx, start, end) \
	FLD_GET(dispc_read_reg(idx), start, end)

#define DISPC_REG_FLD_MOD(idx, val, start, end)				\
	dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))

#define DMM_BASE              0x4E000000
#define DMM_REVISION          0x000
#define DMM_HWINFO            0x004
#define DMM_LISA_HWINFO       0x008
#define DMM_DMM_SYSCONFIG     0x010
#define DMM_LISA_LOCK         0x01C
#define DMM_LISA_MAP__0       0x040
#define DMM_LISA_MAP__1       0x044
#define DMM_TILER_HWINFO      0x208
#define DMM_TILER_OR__0       0x220
#define DMM_TILER_OR__1       0x224
#define DMM_PAT_HWINFO        0x408
#define DMM_PAT_GEOMETRY      0x40C
#define DMM_PAT_CONFIG        0x410
#define DMM_PAT_VIEW__0       0x420
#define DMM_PAT_VIEW__1       0x424
#define DMM_PAT_VIEW_MAP__0   0x440
#define DMM_PAT_VIEW_MAP_BASE 0x460
#define DMM_PAT_IRQ_EOI       0x478
#define DMM_PAT_IRQSTATUS_RAW 0x480
#define DMM_PAT_IRQSTATUS     0x490
#define DMM_PAT_IRQENABLE_SET 0x4A0
#define DMM_PAT_IRQENABLE_CLR 0x4B0
#define DMM_PAT_STATUS__0     0x4C0
#define DMM_PAT_STATUS__1     0x4C4
#define DMM_PAT_STATUS__2     0x4C8
#define DMM_PAT_STATUS__3     0x4CC
#define DMM_PAT_DESCR__0      0x500
#define DMM_PAT_DESCR__1      0x510
#define DMM_PAT_DESCR__2      0x520
#define DMM_PAT_DESCR__3      0x530
#define DMM_PEG_HWINFO        0x608
#define DMM_PEG_PRIO          0x620
#define DMM_PEG_PRIO_PAT      0x640

static u32 fb_addr = 0x7fda8000;

static inline u32 dispc_read_reg(const u32 idx)
{
	return __raw_readl(DISPC_BASE + idx);
}

static inline void dispc_write_reg(const u32 idx, u32 val)
{
	__raw_writel(val, DISPC_BASE + idx);
}

static inline u32 dmm_read_reg(const u32 idx)
{
	return __raw_readl(DMM_BASE + idx);
}

static inline void dmm_write_reg(const u32 idx, u32 val)
{
	__raw_writel(val, DMM_BASE + idx);
}

#define DISPC_DUMPREG(r) printf("%-35s %08x\n", #r, dispc_read_reg(r))

static int board_init_dispc(void)
{
	u32 rev = 0;
    int ret = 0;

	printf("%s, begin\n", __func__);
    dispc_write_reg(DISPC_IRQSTATUS,                0xffffffff);

    dispc_write_reg(DISPC_SYSCONFIG,                0x00002011);

    dispc_write_reg(DISPC_OVL_BA0,                  fb_addr);
    dispc_write_reg(DISPC_OVL_BA1,                  fb_addr);
    dispc_write_reg(DISPC_OVL_POSITION,             0x00000000);
    dispc_write_reg(DISPC_OVL_SIZE,                 0x0257031f);
    dispc_write_reg(DISPC_OVL_ATTRIBUTES,           0x000040b0);
    dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD,       0x07ff07f8);
    dispc_write_reg(DISPC_OVL_ROW_INC,              0x00000001);
    dispc_write_reg(DISPC_OVL_PIXEL_INC,            0x00000001);
    dispc_write_reg(DISPC_OVL_PRELOAD,              0x000007ff);
    dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD,      0x05000400);
    dispc_write_reg(DISPC_OVL_WINDOW_SKIP,          0x00000000);
    dispc_write_reg(DISPC_OVL_TABLE_BA,             0x00000000);

    DISPC_REG_FLD_MOD(DISPC_OVL_ATTRIBUTES, 0x0, 5, 5);
    DISPC_REG_FLD_MOD(DISPC_OVL_ATTRIBUTES, 0xC, 4, 1);
    DISPC_REG_FLD_MOD(DISPC_OVL_ATTRIBUTES, 1, 0, 0);


//DISPC_IRQENABLE                                   0x1694564e
    dispc_write_reg(DISPC_CONTROL,                  0x00018308);
    dispc_write_reg(DISPC_CONFIG,                   0x0000000c);
    dispc_write_reg(DISPC_LINE_NUMBER,              0x00000000);
    dispc_write_reg(DISPC_GLOBAL_ALPHA,             0xffffffff);

    dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,   0x00000001);
    dispc_write_reg(DISPC_DEFAULT_COLOR,            0x00000000);
    dispc_write_reg(DISPC_TRANS_COLOR,              0x00000000);
    dispc_write_reg(DISPC_SIZE_MGR,                 0x0257031f);
    dispc_write_reg(DISPC_TIMING_H,                 0x0570277f);
    dispc_write_reg(DISPC_TIMING_V,                 0x01700103);
    dispc_write_reg(DISPC_POL_FREQ,                 0x00073000);
    dispc_write_reg(DISPC_DIVISORo,                 0x00010005);
    dispc_write_reg(DISPC_DIVISOR,                  0x00010000);
    dispc_write_reg(DISPC_DATA_CYCLE1,              0x00000000);
    dispc_write_reg(DISPC_DATA_CYCLE2,              0x00000000);
    dispc_write_reg(DISPC_DATA_CYCLE3,              0x00000000);
    dispc_write_reg(DISPC_CPR_COEF_R,               0x00000000);
    dispc_write_reg(DISPC_CPR_COEF_G,               0x00000000);
    dispc_write_reg(DISPC_CPR_COEF_B,               0x00000000);

    COM_REG_FLD_MOD(CTRL_CORE_SMA_SW_1, 1, 16, 16);
    COM_REG_FLD_MOD(CTRL_CORE_SMA_SW_1, 1, 22, 22);

	dmm_write_reg(DMM_PAT_VIEW__0,       0x88888888);
	dmm_write_reg(DMM_PAT_VIEW__1,       0x88888888);
//	dmm_write_reg(DMM_PAT_VIEW_MAP__0,   0x80808080);
	dmm_write_reg(DMM_PAT_VIEW_MAP__0,   0x00000000);
	dmm_write_reg(DMM_PAT_VIEW_MAP_BASE, 0x80000000);
	dmm_write_reg(DMM_TILER_OR__0,       0x88888888);
	dmm_write_reg(DMM_TILER_OR__1,       0x88888888);

    DISPC_REG_FLD_MOD(DISPC_CONTROL, 1, 5, 5);

    DISPC_REG_FLD_MOD(DISPC_CONTROL, 1, 0, 0);

#if 0

    ret = do_wait(DISPC_BASE + DISPC_CONTROL, 5, 5, 0, 5000);
    printf("DISPC Wait for DISPC_CONTROL bit 5 to 0, ret:%d\n", ret);
#endif

	rev = dispc_read_reg(DISPC_REVISION);
    printf("OMAP DISPC rev %d.%d\n",
	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));

    DSS_DUMPREG(DSS_REVISION);
    DSS_DUMPREG(DSS_SYSCONFIG);
    DSS_DUMPREG(DSS_SYSSTATUS);
	DSS_DUMPREG(DSS_CONTROL);
	DSS_DUMPREG(DSS_STATUS);

    COM_DUMPREG(PM_DSS_PWRSTCTRL);
    COM_DUMPREG(PM_DSS_PWRSTST);
    COM_DUMPREG(PM_DSS_DSS_WKDEP);
    COM_DUMPREG(RM_DSS_DSS_CONTEXT);
    COM_DUMPREG(PM_DSS_DSS2_WKDEP);
    COM_DUMPREG(RM_DSS_BB2D_CONTEXT);
    COM_DUMPREG(RM_DSS_SDVENC_CONTEXT);

    COM_DUMPREG(CM_DIV_H12_DPLL_PER);
	COM_DUMPREG(CTRL_CORE_CONTROL_IO_2);
	COM_DUMPREG(CM_DSS_CLKSTCTRL);
	COM_DUMPREG(CM_DSS_DSS_CLKCTRL);
	COM_DUMPREG(CTRL_CORE_DSS_PLL_CONTROL);

    COM_DUMPREG(CTRL_CORE_SMA_SW_1);

    DISPC_DUMPREG(DISPC_REVISION);
    DISPC_DUMPREG(DISPC_SYSCONFIG);
    DISPC_DUMPREG(DISPC_SYSSTATUS);
    DISPC_DUMPREG(DISPC_IRQSTATUS);
    DISPC_DUMPREG(DISPC_IRQENABLE);
    DISPC_DUMPREG(DISPC_CONTROL);
    DISPC_DUMPREG(DISPC_CONFIG);
    DISPC_DUMPREG(DISPC_CAPABLE);
    DISPC_DUMPREG(DISPC_LINE_STATUS);
    DISPC_DUMPREG(DISPC_LINE_NUMBER);
    DISPC_DUMPREG(DISPC_DIVISOR);

    DISPC_DUMPREG(DISPC_GLOBAL_ALPHA);
    DISPC_DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
    DISPC_DUMPREG(DISPC_DEFAULT_COLOR);
    DISPC_DUMPREG(DISPC_TRANS_COLOR);
    DISPC_DUMPREG(DISPC_SIZE_MGR);
    DISPC_DUMPREG(DISPC_TIMING_H);
    DISPC_DUMPREG(DISPC_TIMING_V);
    DISPC_DUMPREG(DISPC_POL_FREQ);
    DISPC_DUMPREG(DISPC_DIVISORo);

    DISPC_DUMPREG(DISPC_DATA_CYCLE1);
    DISPC_DUMPREG(DISPC_DATA_CYCLE2);
    DISPC_DUMPREG(DISPC_DATA_CYCLE3);
    DISPC_DUMPREG(DISPC_CPR_COEF_R);
    DISPC_DUMPREG(DISPC_CPR_COEF_G);
    DISPC_DUMPREG(DISPC_CPR_COEF_B);

    DISPC_DUMPREG(DISPC_OVL_BA0);
    DISPC_DUMPREG(DISPC_OVL_BA1);
    DISPC_DUMPREG(DISPC_OVL_POSITION);
    DISPC_DUMPREG(DISPC_OVL_SIZE);
    DISPC_DUMPREG(DISPC_OVL_ATTRIBUTES);
    DISPC_DUMPREG(DISPC_OVL_FIFO_THRESHOLD);
    DISPC_DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS);
    DISPC_DUMPREG(DISPC_OVL_ROW_INC);
    DISPC_DUMPREG(DISPC_OVL_PIXEL_INC);
    DISPC_DUMPREG(DISPC_OVL_PRELOAD);
    DISPC_DUMPREG(DISPC_OVL_MFLAG_THRESHOLD);
    DISPC_DUMPREG(DISPC_OVL_WINDOW_SKIP);
    DISPC_DUMPREG(DISPC_OVL_TABLE_BA);

	printf("%s, end\n", __func__);
    return 0;
}

//int board_display_update_bmp(void *bmp)
int board_display_fill_color(u32 x,
                             u32 y,
                             u32 w,
                             u32 h,
                             u32 color,
                             bool is_gray)
{
    u32 i,j;

    printf("%s, fb_addr:%x\n", __func__, fb_addr);
    printf("%s, x:%u, y:%u, w:%u, h:%u, color:%x\n", __func__, x, y, w, h, color);
    
    if (is_gray == true)
    {
        for (j=y; j<y+h; j++)
        {
            for (i=x; i<x+w; i++)
            {
                u32 t = i % 256;
                *(((u32*)fb_addr) + i + j * 800) = t | (t << 8) | (t <<16);
            }
        }
    }
    else
    {
        for (j=y; j<y+h; j++)
        {
            for (i=x; i<x+w; i++)
            {
                *(((u32*)fb_addr) + i + j * 800) = color;
            }
        }
    }
    return 0;
}

int board_init_display(void)
{
#if 1
    if (board_init_dss())
    {
        return -EINVAL;
    }
    if (board_init_dispc())
    {
        return -EINVAL;
    }
//    board_display_update_bmp(NULL);
#endif
    return 0;
}


/*
 static const struct omap_dss_features omap5_dss_features = {
	.reg_fields = omap5_dss_reg_fields,
	.num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),

	.features = omap5_dss_feat_list,
	.num_features = ARRAY_SIZE(omap5_dss_feat_list),

	.num_mgrs = 4,
	.num_ovls = 4,
	.supported_displays = omap5_dss_supported_displays,
	.supported_outputs = omap5_dss_supported_outputs,
	.supported_color_modes = omap4_dss_supported_color_modes,
	.overlay_caps = omap4_dss_overlay_caps,
	.dss_params = omap5_dss_param_range,
	.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
	.buffer_size_unit = 16,
	.burst_size_unit = 16,
};

static const struct dispc_features omap54xx_dispc_feats = {
	.sw_start		=	7,
	.fp_start		=	19,
	.bp_start		=	31,
	.sw_max			=	256,
	.vp_max			=	4095,
	.hp_max			=	4096,
	.mgr_width_start	=	11,
	.mgr_height_start	=	27,
	.mgr_width_max		=	4096,
	.mgr_height_max		=	4096,
	.max_lcd_pclk		=	170000000,
	.max_tv_pclk		=	186000000,
	.calc_scaling		=	dispc_ovl_calc_scaling_44xx,
	.calc_core_clk		=	calc_core_clk_44xx,
	.num_fifos		=	5,
	.gfx_fifo_workaround	=	true,
	.mstandby_workaround	=	true,
	.set_max_preload	=	true,
	.supports_sync_align	=	true,
	.has_writeback		=	true,
	.supports_double_pixel	=	true,
	.reverse_ilace_field_order =	true,
	.has_gamma_table	=	true,
	.has_gamma_i734_bug	=	true,
};


 */

0 jinhu wu over 8 years ago in reply to jinhu wu

Intellectual 800 points

any suggestion?

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U-Boot/AM572x: DSS/DISPC driver