Hello,
I'm new to the DSP world and am writing some DDR3 init code based on the 6657 Lite EVM code. The DDR part I am using is MT41K256M16 32 Meg x 16 x 8 banks from Micron with a 2k page size.
I've seen where to adjust the page size in the EVM DDR init code (sdramcfg.pageSize = 3; // 3 for 2048 page size), but do not see where to set RAM size in the DDR controller - is this necessary?
I've been cross checking the AC characteristics for setting the three timing registers, and from datasheet to datasheet the characteristics and calculations match - I'm taking this to mean that I can use the timing register values from the EVM provided my PLL values and input clock provide 666.5Mhz, is this correct?
I will be updating the automatic leveling values once I get there, I just want to make sure I have the sizes and basic timing down first. It just seems there isn't much for me to change in this section.
CSL_BootCfgUnlockKicker();
/* Wait for PLL to lock = min 500 ref clock cycles.
With refclk = 100MHz, = 5000 ns = 5us */
platform_delaycycles(50000);
/**************** 3.3 Leveling Register Configuration ********************/
CSL_BootCfgGetDDRConfig(0, &ddr3config);
ddr3config &= ~(0x007FE000); // clear ctrl_slave_ratio field
CSL_BootCfgSetDDRConfig(0, ddr3config);
CSL_BootCfgGetDDRConfig(0, &ddr3config);
ddr3config |= 0x00200000; // set ctrl_slave_ratio to 0x100
CSL_BootCfgSetDDRConfig(0, ddr3config);
CSL_BootCfgGetDDRConfig(12, &ddr3config);
ddr3config |= 0x08000000; // Set invert_clkout = 1
CSL_BootCfgSetDDRConfig(12, ddr3config);
CSL_BootCfgGetDDRConfig(0, &ddr3config);
ddr3config |= 0xF; // set dll_lock_diff to 15
CSL_BootCfgSetDDRConfig(0, ddr3config);
CSL_BootCfgGetDDRConfig(23, &ddr3config);
ddr3config |= 0x00000200; // See section 4.2.1, set for partial automatic levelling
CSL_BootCfgSetDDRConfig(23, ddr3config);
/**************** 3.3 Partial Automatic Leveling ********************/
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(2, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(3, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(4, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(5, ddr3config);
ddr3config = 0x00000033; CSL_BootCfgSetDDRConfig(6, ddr3config);
ddr3config = 0x0000003A; CSL_BootCfgSetDDRConfig(7, ddr3config);
ddr3config = 0x0000002C; CSL_BootCfgSetDDRConfig(8, ddr3config);
ddr3config = 0x0000002C; CSL_BootCfgSetDDRConfig(9, ddr3config);
ddr3config = 0x0000001C; CSL_BootCfgSetDDRConfig(10, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(14, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(15, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(16, ddr3config);
ddr3config = 0x00; CSL_BootCfgSetDDRConfig(17, ddr3config);
ddr3config = 0x000000B7; CSL_BootCfgSetDDRConfig(18, ddr3config);
ddr3config = 0x000000B1; CSL_BootCfgSetDDRConfig(19, ddr3config);
ddr3config = 0x000000A4; CSL_BootCfgSetDDRConfig(20, ddr3config);
ddr3config = 0x000000A4; CSL_BootCfgSetDDRConfig(21, ddr3config);
ddr3config = 0x00000098; CSL_BootCfgSetDDRConfig(22, ddr3config);
/*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */
CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
ddrPhyCtrl &= ~(0x00008000);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
ddrPhyCtrl |= (0x00008000);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
ddrPhyCtrl &= ~(0x00008000);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
/***************** 3.4 Basic Controller and DRAM configuration ************/
/* enable configuration */
/* hEmif->SDRAM_REF_CTRL = 0x00006180; */
CSL_EMIF4F_EnableInitRefresh();
CSL_EMIF4F_SetRefreshRate(0x515C);
sdram_tim1.t_wtr = 4;
sdram_tim1.t_rrd = 1;
sdram_tim1.t_rc = 0x20;
sdram_tim1.t_ras = 0x17;
sdram_tim1.t_wr = 0x09;
sdram_tim1.t_rcd = 0x09;
sdram_tim1.t_rp = 0x09;
CSL_EMIF4F_SetTiming1Config(&sdram_tim1);
/* hEmif->SDRAM_TIM_2 = 0x40877FEC; */
sdram_tim2.t_cke = 3;
sdram_tim2.t_rtp = 4;
sdram_tim2.t_xsrd = 0x1FF;
sdram_tim2.t_xsnr = 0x071;
sdram_tim2.t_xp = 3;
sdram_tim2.t_odt = 0;
CSL_EMIF4F_SetTiming2Config (&sdram_tim2);
/* hEmif->SDRAM_TIM_3 = 0x55BF87FF; */
sdram_tim3.t_rasMax = 0xF;
sdram_tim3.t_rfc = 0x06A;
sdram_tim3.t_tdqsckmax = 0;
sdram_tim3.zq_zqcs = 0x3F;
sdram_tim3.t_ckesr = 4;
sdram_tim3.t_csta = 0x5;
sdram_tim3.t_pdll_ul = 0x5;
CSL_EMIF4F_SetTiming3Config (&sdram_tim3);
/* hEmif->DDR_PHY_CTRL_1 = 0x0010010F; */
ddrPHYReadLatency = 0x0F;
ddrPhyCtrl = (0x0010010F);
CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
/* hEmif->ZQ_CONFIG = 0x70074C1F; */
zqcfg.zqRefInterval = 0x4C1F;
zqcfg.zqZQCLMult = 3;
zqcfg.zqZQCLInterval = 1;
zqcfg.zqSFEXITEn = 1;
zqcfg.zqDualCSEn = 1;
zqcfg.zqCS0En = 1;
zqcfg.zqCS1En = 0;
CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);
/* hEmif->PWR_MGMT_CTRL = 0x0; */
pwrmgmtcfg.csTime = 0;
pwrmgmtcfg.srTime = 0;
pwrmgmtcfg.lpMode = 0;
pwrmgmtcfg.dpdEnable = 0;
pwrmgmtcfg.pdTime = 0;
CSL_EMIF4F_SetPowerMgmtConfig (&pwrmgmtcfg);
/* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */
/* hEmif->SDRAM_CONFIG = 0x63077AB3; */
CSL_EMIF4F_GetSDRAMConfig (&sdramcfg);
sdramcfg.pageSize = 3; // 3 for 2048 page size
sdramcfg.eBank = 0;
sdramcfg.iBank = 3;
sdramcfg.rowSize = 5;
sdramcfg.CASLatency = 14;
sdramcfg.narrowMode = 1;
sdramcfg.CASWriteLat = 3;
sdramcfg.SDRAMDrive = 1;
sdramcfg.disableDLL = 0;
sdramcfg.dynODT = 2;
sdramcfg.ddrDDQS = 0;
sdramcfg.ddrTerm = 2;
sdramcfg.iBankPos = 0;
sdramcfg.type = 3;
CSL_EMIF4F_SetSDRAMConfig (&sdramcfg);
pll_delay(840336); /*Wait 600us for HW init to complete*/
/* Refresh rate = (7.8*666MHz] */
/* hEmif->SDRAM_REF_CTRL = 0x00001450; */
CSL_EMIF4F_SetRefreshRate(0x0000144F);
/***************** 4.2.1 Partial automatic leveling ************/
/* hEmif->RDWR_LVL_RMP_CTRL = 0x80000000; */
CSL_EMIF4F_SetLevelingRampControlInfo(1, 0, 0, 0, 0);
/* Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value */
/* hEmif->RDWR_LVL_CTRL = 0x80000000; */
CSL_EMIF4F_SetLevelingControlInfo(1, 0, 0, 0, 0);
/************************************************************
Wait for min 1048576 DDR clock cycles for leveling to complete
= 1048576 * 1.5ns = 1572864ns = 1.57ms.
Actual time = ~10-15 ms
**************************************************************/
pll_delay(4201680); //Wait 3ms for leveling to complete
return (status);
