TMS320C6746: C6746 EDMA: DMAQNUMn

Hi Parul,

I've forwarded your query to the software experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Parul,

This particular TI documentation is not at its best. 'n' is used in both tables to represent different values. In some of our newer documentation we have been more clear by using x and y to denote different enumerated values. In this case, DMAQNUMx should be used and the numbers across the top of Table 16-28 represent the value to be used for x. For example, E8 goes with bits 0-2 in DMAQNUM1.

The Enum values in Table 16-28 represent the channels that are assigned to a specific Event. In your case, you are using E12 and E13.

I am not sure which CSL commands are available or recommended in the latest Processor SDK release, but if you are not using that, I recommend you move to it for the best ongoing support and portability across all of our recent processors.

Personally, I dislike using the FINS/FINST functions because they do read/modify/write operations. This is not a problem if this code is only done once during setup, but RMW on EDMACC registers is slow and can cause problems when used during a realtime processing application.

You can see from my explanation that your arguments for the FINST need to be updated to use the right En field masks; that is what the EDMA3CC_DMAQNUM_E0 is used for.

Where did you get an example for this code?

I do not know what the right token or field values would be for the version of CSLr you are using, so I recommend you look for examples in the ProcSDK. Otherwise, look through the CSL source code to figure out what FINST needs.

Regards,
RandyP

Hi Randy,

I have this version of CSL
software-dl.ti.com/.../index_FDS.html.

The cslr_edma3cc.h flie has token for DMAQNUM, which where CSL_FINST gets the token from. The file has the following tokens for DMAQNUM:

/* DMAQNUM */


#define CSL_EDMA3CC_DMAQNUM_E7_MASK (0x70000000u)
#define CSL_EDMA3CC_DMAQNUM_E7_SHIFT (0x0000001Cu)
#define CSL_EDMA3CC_DMAQNUM_E7_RESETVAL (0x00000000u)
/*----E7 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E7_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E7_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E6_MASK (0x07000000u)
#define CSL_EDMA3CC_DMAQNUM_E6_SHIFT (0x00000018u)
#define CSL_EDMA3CC_DMAQNUM_E6_RESETVAL (0x00000000u)
/*----E6 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E6_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E6_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E5_MASK (0x00700000u)
#define CSL_EDMA3CC_DMAQNUM_E5_SHIFT (0x00000014u)
#define CSL_EDMA3CC_DMAQNUM_E5_RESETVAL (0x00000000u)
/*----E5 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E5_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E5_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E4_MASK (0x00070000u)
#define CSL_EDMA3CC_DMAQNUM_E4_SHIFT (0x00000010u)
#define CSL_EDMA3CC_DMAQNUM_E4_RESETVAL (0x00000000u)
/*----E4 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E4_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E4_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E3_MASK (0x00007000u)
#define CSL_EDMA3CC_DMAQNUM_E3_SHIFT (0x0000000Cu)
#define CSL_EDMA3CC_DMAQNUM_E3_RESETVAL (0x00000000u)
/*----E3 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E3_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E3_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E2_MASK (0x00000700u)
#define CSL_EDMA3CC_DMAQNUM_E2_SHIFT (0x00000008u)
#define CSL_EDMA3CC_DMAQNUM_E2_RESETVAL (0x00000000u)
/*----E2 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E2_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E2_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E1_MASK (0x00000070u)
#define CSL_EDMA3CC_DMAQNUM_E1_SHIFT (0x00000004u)
#define CSL_EDMA3CC_DMAQNUM_E1_RESETVAL (0x00000000u)
/*----E1 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E1_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E1_Q1 (0x00000001u)



#define CSL_EDMA3CC_DMAQNUM_E0_MASK (0x00000007u)
#define CSL_EDMA3CC_DMAQNUM_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E0_RESETVAL (0x00000000u)
/*----E0 Tokens----*/
#define CSL_EDMA3CC_DMAQNUM_E0_Q0 (0x00000000u)
#define CSL_EDMA3CC_DMAQNUM_E0_Q1 (0x00000001u)


#define CSL_EDMA3CC_DMAQNUM_RESETVAL (0x00000000u)


Clearly the tokens are till E7 only . So I am not sure which tokens to use for E12 and E13.

Parul,

The oldest BIOSPSP version that I have locally is 03_10_01_00 in which the file dates are from 2012. Are you supporting a very old product? If not, please upgrade to the latest Processor SDK.

Does your code compile and link correctly as it stands today? The FINST macro requires precise text values in order to resolve to valid tokens. I did not find an example in my old files. What example did you use to come up with your code?

If you locate the definition of the FINST macro, you will see how it creates a set of register operation values: register name, shift count and/or mask value, and insertion value. You have selected the register name using DMAQNUM[ EDMA_QUEUE_RX_UART1 ].

When you look at Table 16-28 and the register drawing above it (in the TRM), you see that you have selected the n=1 column for DMAQNUM so you are selecting from the Eventn values shown there. What you need to select is E12 & E13 to get the correct fields shown on the far-left column. Since you have noticed that the CSL only provides MASK & Shift values for E0-E7, it is implied that you are expected to choose from those to select the corresponding fields for your Events, E12 & E13. Those would be E4 and E5, respectively, correct?

Using your old values of E0 & E1, you can examine the DMAQNUMn registers in CCS before executing those lines and again after stepping over those lines. This will let you see which En fields your code sets. Then update to the new values of E4 & E5 and run it again. Do you see the correct fields being updated this time?

Regards,
RandyP

Hi Randy,

Parul is helping me out with adding UART EDMA support for an existing application, which is already using EDMA for the McASP.  The code she references was created long ago, as you've noticed, using previous SDX/CSL APIs, etc.  We're working on updating the project to the latest SYS-BIOS, but in parallel, we also have to continue integrating UART EDMA support into this version of the project code, without any large scale updates to the support software (CSL).

I've reviewed this thread, and believe what you suggested has worked.  I've attached a picture of the running the suggested DMAQNUM commands, using the old CSL FINST, and a value of E4 and E5, per table 16-28, and it appears to show the correct result.  Before stepping over these three lines (the first is the RX queuing for McASP in 0, just for reference):

CSL_FINST( EDMA3->DMAQNUM[ EDMA_QUEUE_RX ], EDMA3CC_DMAQNUM_E0, Q0 ); 

CSL_FINST( EDMA3->DMAQNUM[ 1 ], EDMA3CC_DMAQNUM_E4, Q1 );
CSL_FINST( EDMA3->DMAQNUM[ 1 ], EDMA3CC_DMAQNUM_E5, Q1 );

I set both DMAQNUM0 and DMAQNUM1 to 0x77777777.  Then I stepped over them, and see 0 in DMAQNUM0 E0, and 1 in DMAQNUM1 E4 and E5 (representing events E12 and E13, per table 16-28).

In this respect, we've configured to queue the UART Tx and Rx events, in dma queue 1.  Would you agree?

Thanks,

Robert