AM5728: GPMC read latency

Hi Shin-san,

Thank you for quick reply.

Our customers seems that most of their applications are single-access GPMC.
Therefore it is not to use the burst access and DMA and NEON.

The introduction thread seems to recommend using DMA, so it seems to be different from this problem.
Depending on the amount of code, delay in GPMC access is a problem.
Is there any other information?

Best Regards,
Shigehiro Tsuda

Tsuda-san,

We have recently added GPMC driver support for Sitara device AM335x and AM437x in Processor SDK RTOS.

I am providing a code snippet of RTOS configuration for access parallel NOR that you can use as reference ( AM355x configuration is provided below)

Cache MMU settings on the ARM for your reference:

/* ================ Cache and MMU configuration ================ */

var Cache = xdc.useModule('ti.sysbios.family.arm.a9.Cache');
Cache.enableCache = true;
Cache.configureL2Sram = false;//DDR build

var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');
Mmu.enableMMU = true;

/* Force peripheral section to be NON cacheable strongly-ordered memory */
var peripheralAttrs = {
    type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
    tex: 0,
    bufferable : false,                // bufferable
    cacheable  : false,                // cacheable
    shareable  : false,                // shareable
    noexecute  : true,                 // not executable
};

/* Define the base address of the 1 Meg page the peripheral resides in. */
var norBaseAddr1 = 0x08000000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(norBaseAddr1,
                          norBaseAddr1,
                          peripheralAttrs);                                                      

/* Define the base address of the 1 Meg page the peripheral resides in. */
/* var norBaseAddr2 = 0x09100000; */
var norBaseAddr2 = 0x08100000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(norBaseAddr2,
                          norBaseAddr2,
                          peripheralAttrs);    

/* Define the base address of the 1 Meg page the peripheral resides in. */
var gpmcBaseAddr = 0x50000000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(gpmcBaseAddr,
                          gpmcBaseAddr,
                          peripheralAttrs);                                                      

Hope this helps.

Regards,

Rahul

Hi Shin-san,

Thank you for quick reply.

If there is a lot of single access to FPGA and they want to realize as fast access as possible, which of the following should be better for GPMC?
1. Set as cache area
2. Set as non-cacheable area

In the case of Rahul-san's answer NOR flash setting, it seems that it is set as non-cache and strongly-ordered memory area.

The wiki site of your introduction has the following description.
· Set as cache area
· Using multiple load instructions

Best Regards,
Shigehiro Tsuda