CCS/DP83867IR: RJ45 LED does not work when connecting cable

Part Number: DP83867IR

Tool/software: Code Composer Studio

Hi~

I did not get enough reply from the previous question.

I am using k2gICE board with ccsv7.

When the reset button is pressed, the LED does not blink on the RJ45 port.

Do I need additional processing to initialize the DP83867 phy chip?

CCS can not read the register value using the script in the provided Gel file.

#define MDIO_CTL *(unsigned int*)(0x4200F00 + 0x04)
#define MDIO_PHY_REG *(unsigned int*)(0x4200F00 + 0x80)
#define PADCONFIG98 *(unsigned int*)(CHIP_LEVEL_REG + 0x1188)
#define PADCONFIG99 *(unsigned int*)(CHIP_LEVEL_REG + 0x118C)

MDIO_Init()
{
    MDIO_CTL = 0x411400ff;
    GEL_TextOut( "MDIO is enabled\n");
    //MDIO_CLK_PADCONFIG= DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_00, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_UP, DEVICE_PIN_MUX_PULL_ENABLE, DEVICE_PIN_MUX_MODE_PRIMARY)
    PADCONFIG98 = 0x00060000;
    //MDIO_DATA_PADCONFIG= DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_00, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_UP,    DEVICE_PIN_MUX_PULL_ENABLE, DEVICE_PIN_MUX_MODE_PRIMARY)
    PADCONFIG99 = 0x00020000;

    GEL_TextOut( "MDIO pinmux is enabled\n");
}

/* Reads Gigabit Ethernet PHY registers to verify the strapping configurations */
hotmenu ReadEth0PHYRegs()
{
    unsigned phy_addr = 0;
    unsigned reg_addr = 0;
    unsigned MDIO_useraccess = 0x04200F80;
    unsigned long temp;

    MDIO_Init();
    GEL_TextOut( "Gig Eth MDIO PHY settings are as follows \n");
    for(reg_addr=0;reg_addr<16;reg_addr++)
    {
        WR_MEM_32(MDIO_useraccess,(reg_addr << 21) | (phy_addr << 16));
        //write same value with GO bit
        WR_MEM_32(MDIO_useraccess,(0x80000000) | (reg_addr << 21) |  (phy_addr << 16));
        temp = (RD_MEM_32(MDIO_useraccess));
        if((temp & 0x20000000) == 0x20000000)
            GEL_TextOut("PHY REG %x = %x\n",,,,,reg_addr,(temp & 0xFFFF));
        else
            GEL_TextOut("PHY REG %x read fail\n",,,,,reg_addr);
    }

    //Additional read of register at addr 0x6E to read Strap Configuration Status Register 1
    reg_addr = 0x6E;
    WR_MEM_32(MDIO_useraccess,(reg_addr << 21) | (phy_addr << 16));
    //write same value with GO bit
    WR_MEM_32(MDIO_useraccess,(0x80000000) | (reg_addr << 21) |  (phy_addr << 16));
    temp = (RD_MEM_32(MDIO_useraccess));
    if((temp & 0x20000000) == 0x20000000)
           GEL_TextOut("PHY REG %x = %x\n",,,,,reg_addr,(temp & 0xFFFF));
    else
           GEL_TextOut("PHY REG %x read fail\n",,,,,reg_addr);

    GEL_TextOut( " Gig Eth PHY0 Boot strap settings are as follows \n");

    //Additional read of register at address 0x6E to read Strap Latch-In Register #1
    reg_addr = 0xD;
    WR_MEM_32(MDIO_useraccess,(reg_addr << 21) | (phy_addr << 16)| 0x001F);
    //write same value with GO bit
    WR_MEM_32(MDIO_useraccess,(0xC0000000) | (reg_addr << 21) |  (phy_addr << 16) | 0x001F);

    reg_addr = 0xE;
    WR_MEM_32(MDIO_useraccess,(reg_addr << 21) | (phy_addr << 16)| 0x6E);
    //write same value with GO bit
    WR_MEM_32(MDIO_useraccess,(0xC0000000) | (reg_addr << 21) |  (phy_addr << 16) | 0x6E);

    reg_addr = 0xD;
    WR_MEM_32(MDIO_useraccess,(reg_addr << 21) | (phy_addr << 16)| 0x401F);
    //write same value with GO bit
    WR_MEM_32(MDIO_useraccess,(0xC0000000) | (reg_addr << 21) |  (phy_addr << 16) | 0x401F);

    reg_addr = 0xE;
    WR_MEM_32(MDIO_useraccess,(reg_addr << 21) | (phy_addr << 16));
    //write same value with GO bit
    WR_MEM_32(MDIO_useraccess,(0x80000000) | (reg_addr << 21) |  (phy_addr << 16));

    temp = (RD_MEM_32(MDIO_useraccess));

    if((temp & 0x20000000) == 0x20000000)
        GEL_TextOut("PHY REG %x = %x\n",,,,,0x6E,(temp & 0xFFFF));
    else
        GEL_TextOut("PHY REG %x read fail\n",,,,,0x6E);
}