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am3358: GPMC throughput

Jeff Coletti
Expert 8755 points
Part Number: AM3358

HI Support team

I need your help with this old e2e which was never closed https://e2e.ti.com/support/arm/sitara_arm/f/791/t/253288

We left off with this question

They are looking to achieve greater than 100MBs on the AM335x using GPMC & DMA+burst transfer. With your experience using GPMC and DMA+Burst transfer, is this data rate feasible? If not could you tell me what the limitation is?

If it is possible, what is necessary/required to achieve the greater than 100MBs? What can they use to move further?

Thanks

Jeff Coletti

  • 0
    TI__Guru**** 393215 points
    Hi Jeff,

    The GPMC functional clock maximum frequency is 100MHz. A If you use 16-bit burst access you will need roughly at least 5 clock cycles for GPMC address phase plus 1 clock cycle for each 16-bit transfer. 16 words is the largest burst size, which would take at least 21 cycles for 32 bytes, or 21ns.

    100MBytes will take (100 000 000 / 32) * 0.00000021 = 0.66 seconds to complete.

    However these are only rough calculations. In a real use case there will be other tasks to perform too. I will ask the factory team to comment too. They will post here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 87040 points
    Jeff, i think Biser's calculation is a pretty good estimate of optimal performance out of the hardware. I think you would have to add some more time for software overhead, so 100MB/s might be the best you could achieve. And the GPMC interface would have to be dedicated to the FPGA.

    The post you point to mentions issues with getting DMA and GPMC burst mode to work concurrently, but i am not aware of any issues with regard to that. Certainly, both would need to work together to get the best performance.

    Do you need that performance for read, write, or both?

    Regards,
    James
  • 0 in reply to JJD
    Prodigy 10 points
    For this product we are looking for high DMA performance for read from FPGA only.
    Thanks for trying to help.

    Regards
    Leonid
  • 0 in reply to Leonid Volpert8
    TI__Guru* 87040 points
    Hi Leonid,
    ok, so you will want to optimize the accesses much like the timing diagram in figure 7-19 in the TRM. You should be able to get 16 word bursts, but you would have to optimize the cycle to cycle delays, and also the addressing cycle. Conservatively, if you add more overhead for this (say 10 cycles instead of 5), you should be able to achieve 32Bytes in 260ns, or 123MB/s.

    Also read section 7.1.2.3.10.5 "System Burst Vs External Device Burst Support" for other consideration you many need to take into account.

    Small typo above in Biser's post, should be 210ns, not 21ns

    Regards,
    james