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RTOS/AM5728: PCIe link issue

henry kim
Intellectual 590 points

Part Number: AM5728
Other Parts Discussed in Thread: SYSCONFIG

Tool/software: TI-RTOS

Hi,

 

There are some issues on PCIe.

 

The customer connects FPGA to Port #1 of 2 PCIe Ports(#0 and #1) on AM5728 and there is communication between DSP and FPGA.

 

They removed PCIe Port #0 source code using for Port #0 so there is link issue on PCIe Port #1.

 

So I have some questions as below.

 

1. Is PCIe #1 communication available when PCIe #0 is activated on AM5728?

(I wonder the other Ports communication is available like ARM Core when the main PCIe Port is activated.)

 

2. Is PCIe Port #0 source code removed properly as below?

> The removal of DSP_PCIESPACE_SS1 area and DSP_PCIEREG_SS1 area from the resource table.

> The removal of below functions from pcieSerdesCfg function.

(PlatformPCIESS1ClockEnable, PlatformPCIESS1PllConfig, PlatformPCIESS1CtrlConfig, PlatformPCIESS1Reset, PlatformPCIESS1PhyConfig)

 

3. Is PCIe Packet extension is available?

> Only 4bytes of PCIe Packet Data is transmitted at once, so is it possible to extend or change of Packet Data?

 

I attached the log as below.

The log when PCIe Port #0 is removed and there is link issue on Port #1. : PCIe1port_LinkERR.TXT

The log when Port #0 is activated and Port #1 is linked. : PCIe1port_LinkOK.TXT

 

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points

    Hi,

    From the AM5728x TRM Table 26-61. PCIePHY Subsystem Low-Level Programming Sequence:

    Start a software forced wake-up transition on the PCIE

    clock domain

    CM_PCIE_CLKSTCTRL[1:0] CLKTRCTRL 0x2

    Start a software forced wake-up transition on the

    L3INIT clock domain

    CM_L3INIT_CLKSTCTRL[1:0] CLKTRCTRL 0x2

    Configure the PCIESS1 module to be explicitly

    enabled

    CM_PCIE_PCIESS1_CLKCTRL[1:0] MODULEMODE 0x2

    Poll for PCIESS1 module fully functional? CM_PCIE_PCIESS1_CLKCTRL[17:16] IDLEST =0x0

    Optional: Configure the PCIESS2 module to be

    explicitly enabled

    CM_PCIE_PCIESS2_CLKCTRL[1:0] MODULEMODE 0x2

    Optional: Poll for PCIESS2 module fully functional? CM_PCIE_PCIESS2_CLKCTRL[17:16] IDLEST =0x0

    Configure the OCP2SCP3 module to be managed

    automatically by hardware according to clock domain

    transition

    CM_L3INIT_OCP2SCP3_CLKCTRL[1:0]

    MODULEMODE

    0x1

    Perform a software reset on OCP2SCP3 OCP2SCP_SYSCONFIG[1] SOFTRESET 1

    Wait until reset is finished? OCP2SCP_SYSSTATUS[0] RESETDONE =1

    Configure the

    ....

    That is, you have to enable PCIESS1 even you only intend to use PCIESS2. At least below two are required:

    PlatformPCIESS1ClockEnable();
    PlatformPCIESS1PllConfig();

    The rest three you can try if can be removed:

    PlatformPCIESS1CtrlConfig();
    PlatformPCIESS1Reset();
    PlatformPCIESS1PhyConfig();

    My suggestion is to keep the PCIESS1 code there, even you don't use that port. 

    Regards, Eric