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Linux/AM3356: GPIO control issue

Part Number: AM3356
Other Parts Discussed in Thread: TPS65910

Tool/software: Linux

One of our applications required gpmc_be1n to be used as gpio pin, initially the pinmux details reflected that the pin mode is set as 0x00000008 which means its not configured as gpio(MUX Mode 0x7). Hence, I modified the dts file to enable the pin as gpio in the pin mux. Having done this, pinmux details reflect our change i.e mode changed to 0x00000037. (cat pins (sys/kernel/debug/pinctrl/44e10878.pinmux))

I did the following:(using sysfs)

echo 60 > export

echo "out " > gpio60/direction

echo 0 > gpio60/value

but when probed the pin it was always in the high state. I could control other pins using the sysfs interface after the dts changes (gpio3_13, gpio3_20 etc whose default pinmux was set to 0x00000020 and with the modified dts it was 0x00000037 )

I was able to control the pin from Uboot using gpio commands as well. (here pinmux i modified using mw 0x44e10878 w 0x00000037)

And from the linux , I tried to use devmem2 to write the gpio register

devmem2  0x4804c134 w 0xEFFDFFFF

devmem2  0x4804c13C w 0x00000000

This made the pin to change the state to low on probing.

So can any one help me in finding out the issue with the sysfs interfaces on the pin? below is the dts modification i have made

am33xx_pinmux: pinmux@44e10800 {
        pinctrl-names = "default";

...

gpio1_pins: pinmux_gpio1_pins {
            pinctrl-single,pins = <
                0x78 (0x37)  /* gpio1_28,conf_gpmc_ben1*/
            >;
        };

gpio3_pins: pinmux_gpio3_pins { /*Added by SVR*/
                        pinctrl-single,pins = <
                                  0x1A8 (0x37)  /* gpio3_20,conf_mcasp0 */
                                0x234 (0x37) /* gpio3_13,conf_usb1_drvvbu */
                        >;
                };
...   

};

...

&gpio1 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio1_pins>;
    status = "okay";
};

&gpio3 {
        pinctrl-names = "default";
        pinctrl-0 = <&gpio3_pins>;
        status = "okay";
};

  • Hello Sai,

    There are few suspicious points to check. This pin might be pinmuxed in U-Boot, see this and this thread, or it is not pinmuxed at all, like in this case. Another point is that you might calculate the gpio number improperly like in this and this thread.

    Best regards,
    Kemal

  • Hi Kemal,

    Thanks for the reply.

    When I have set the pinmux of gpmc_be1n(gpio1_28) pin to MUX-Mode 7 in uboot source code ( u-boot-<version>/board/ti/am335x/mux.c ) without modifying the dts file to set the same(  pin as Mode 7 ), I'm able to control the gpio using sysfs !!

    But I would like to set the same using dts file rather than in uboot. Also, when pinmuxed the gpio1_28 pin as Mode 7 in both uboot and dts file, I'm not able to control it through sysfs. Whether issue is in the way I'm doing in dts file ? but with the similar kind of changes in dts file I'm able to control other gpio's ( gpio3_13, gpio3_20 ).

    Can you please help me in resolving this issue.

  • gpmc_ben1.gpio1_28 is already pinmuxed as gpmc_ben1.mmc2_dat3 in <Processor SDK>/board-support/u-boot-<version>/arch/arm/dts/am335x-evm.dts. Do not you see it?
     
        mmc3_pins: pinmux_mmc3_pins {
            pinctrl-single,pins = <
                0x44 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
                0x48 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
                0x4C (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
                0x78 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
                0x88 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
                0x8C (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
            >;
        };

  • I am  not using the am335x-evm.dts for our application. In both am335x.dtsi and dts file(which i have edited for our applications), it is ensured that the pinmux for the respective pins are not provided anywhere else other than pinmux_gpio1_pins which I have added for the support as mentioned in my first comment.

    Also as you said , will uboot use the device tree binary for pinmuxing? I was under the impression that only linux uses the same.  I understand uboot uses the configuration provided in the mux.c file for setting up pin mux regs.

    My current status : After adding pin mux configuration in mux.c in uboot, the gpio control is possible using sys/class/gpio. In this case linux dts has no pinmux overlay for the GPIO1_28 (gpmc_be1n).

    When I add the same in dts file, with/without changes in uboot, the gpio control is not working.

  • /*
     * Copyright (C) 2012 Texas Instruments Incorporated - <a href="http://www.ti.com/">http://www.ti.com/</a>
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */

    /*
     * AM335x Starter Kit
     * <a href="http://www.ti.com/tool/tmdssk3358">www.ti.com/.../tmdssk3358</a>
     */

    /dts-v1/;

    #include "am33xx.dtsi"

    / {
        model = "TI AM335x SYNC-OEM";
        compatible = "ti,am335x-evmsk", "ti,am33xx";

        cpus {
            cpu@0 {
                cpu0-supply = <&vdd1_reg>;
            };
        };

        memory {
            device_type = "memory";
            reg = <0x80000000 0x10000000>; /* 256 MB */
        };

        am33xx_pinmux: pinmux@44e10800 {
            pinctrl-names = "default";
            

            i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
                    0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
                    0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
                >;
            };
            
            i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
                    0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
                    0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
                >;
            };
            
            i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
                    0x150 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_sclk.i2c0_sda */
                    0x154 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d0.i2c0_scl */
                >;
            };
            dcan1_pins: pinmux_dcan1_pins {
            pinctrl-single,pins = <
                    0x100 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mmc0_clk.dcan1_txd */
                    0x104 (PIN_INPUT | MUX_MODE4)       /* mmc0_cmd.dcan1_rxd */
                >;
            };

                gpio1_pins: pinmux_gpio1_pins{ /*This doesnt work*/
                pinctrl-single,pins = <
                    0x78 (0x37)/*(PIN_OUTPUT | MUX_MODE7)*/ /* gpio1_28,conf_gpmc_ben1*/
                >;
            };
                gpio3_pins: pinmux_gpio3_pins {/*This works*/
                            pinctrl-single,pins = <
                    0x1A8 (0x37) /* (PIN_OUTPUT | MUX_MODE7)*/ /* gpio3_20,conf_mcasp0 */
                                    0x234 (0x37) /*(PIN_OUTPUT | MUX_MODE7)*/ /* gpio3_13,conf_usb1_drvvbu*/
                            >;
                    };

            uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
                    0x168 (PIN_INPUT | MUX_MODE0)       /* uart0_ctsn.uart0_ctsn */
                    0x16C (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart0_rtsn .uart0_rtsn  */
                    0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
                    0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
                >;
            };
            uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
                    0x178 (PIN_INPUT | MUX_MODE0)       /* uart1_ctsn.uart1_ctsn */
                    0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
                    0x180 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
                    0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */  
                    0xFC (PIN_INPUT | MUX_MODE4)        /* mmc0_dat0.uart1_ri */
                    0xF8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* mmc0_dat0.uart1_dtr */
                    0xF4 (PIN_INPUT | MUX_MODE4)        /* mmc0_dat0.uart1_dsr */
                    0xF0 (PIN_INPUT | MUX_MODE4)        /* mmc0_dat0.uart1_dcd */
                >;
            };
            
            uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
                    0x164 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.UART3_TXD */
                    0x160 (PIN_INPUT_PULLUP | MUX_MODE1)    /* spi0_cs1.UART3_RXD */
                    0xCC (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* LCD_DATA11.UART3_RTSN */
                    0xC8 (PIN_INPUT | MUX_MODE6)        /* LCD_DATA10.UART3_CTSN */
                >;
            };
            uart5_pins: pinmux_uart5_pins {
                pinctrl-single,pins = <
                    0xD8 (PIN_INPUT | MUX_MODE6)        /* lcd_data14.uart5_ctsn */
                    0xDC (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* lcd_data15.uart5_rtsn */
                    0xC4 (PIN_INPUT_PULLUP | MUX_MODE4) /* lcd_data9.uart5_rxd */
                    0xC0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* lcd_data8.uart5_txd */
                >;
            };
            spi1_pins: pinmux_spi1_pins {
                pinctrl-single,pins = <
                    0x108 (PIN_OUTPUT_PULLUP | MUX_MODE2)   /* mcasp0_aclkx.spi1_sclk, OUTPUT_PULLUP | MODE2 */
                    0x10C (PIN_INPUT_PULLUP | MUX_MODE2)    /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE2 */
                    0x110 (PIN_OUTPUT_PULLUP | MUX_MODE2)   /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE2 */
                    0x144 (PIN_OUTPUT_PULLUP | MUX_MODE2)   /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE2 */
                >;
            };
            nandflash_pins_default: nandflash_pins_default {
                pinctrl-single,pins = <
                    0x0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* gpmc_ad0.gpmc_ad0 */
                    0x4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* gpmc_ad1.gpmc_ad1 */
                    0x8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* gpmc_ad2.gpmc_ad2 */
                    0xc (PIN_INPUT_PULLUP | MUX_MODE0)  /* gpmc_ad3.gpmc_ad3 */
                    0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
                    0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
                    0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
                    0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
                    0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
                    0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
                    0x7c (PIN_OUTPUT | MUX_MODE0)       /* gpmc_csn0.gpmc_csn0  */
                    0x90 (PIN_OUTPUT | MUX_MODE0)       /* gpmc_advn_ale.gpmc_advn_ale */
                    0x94 (PIN_OUTPUT | MUX_MODE0)       /* gpmc_oen_ren.gpmc_oen_ren */
                    0x98 (PIN_OUTPUT | MUX_MODE0)       /* gpmc_wen.gpmc_wen */
                    0x9c (PIN_OUTPUT | MUX_MODE0)       /* gpmc_be0n_cle.gpmc_be0n_cle */
                >;
            };

            nandflash_pins_sleep: nandflash_pins_sleep {
                pinctrl-single,pins = <
                    0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
            };


            cpsw_default: cpsw_default {
                pinctrl-single,pins = <
                    /* Slave 1 */
                    0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
                    0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
                    0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
                    0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
                    0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
                    0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
                    0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
                    0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
                    0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
                    0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
                    0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
                    0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */

                    /* Slave 2 */
                    0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a0.rgmii2_tctl */
                    0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a1.rgmii2_rctl */
                    0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a2.rgmii2_td3 */
                    0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a3.rgmii2_td2 */
                    0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a4.rgmii2_td1 */
                    0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a5.rgmii2_td0 */
                    0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a6.rgmii2_tclk */
                    0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a7.rgmii2_rclk */
                    0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a8.rgmii2_rd3 */
                    0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a9.rgmii2_rd2 */
                    0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a10.rgmii2_rd1 */
                    0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a11.rgmii2_rd0 */
                >;
            };

            cpsw_sleep: cpsw_sleep {
                pinctrl-single,pins = <
                    /* Slave 1 reset value */
                    0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)

                    /* Slave 2 reset value*/
                    0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
            };

            davinci_mdio_default: davinci_mdio_default {
                pinctrl-single,pins = <
                    /* MDIO */
                    0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
                    0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)           /* mdio_clk.mdio_clk */
                >;
            };

            davinci_mdio_sleep: davinci_mdio_sleep {
                pinctrl-single,pins = <
                    /* MDIO reset value */
                    0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
            };

        };

        ocp {
            uart0: serial@44e09000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart0_pins>;
                status = "okay";
                rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                rs485-rts-active-high;
                rs485-rts-delay = <2 1>;
                linux,rs485-enabled-at-boot-time;           

            };

            uart1: serial@48022000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart1_pins>;
                status = "okay";
            };


            uart3: serial@481a6000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart3_pins>;
                status = "okay";
                rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
                rs485-rts-active-high;
                rs485-rts-delay = <2 1>;
                linux,rs485-enabled-at-boot-time;           

            };

            uart5: serial@481aa000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart5_pins>;
                status = "okay";
                rts-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
                rs485-rts-active-high;
                rs485-rts-delay = <2 1>;
                linux,rs485-enabled-at-boot-time;           

            };

            i2c0: i2c@44e0b000 {
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_pins>;

                status = "okay";
                clock-frequency = <400000>;
                /* Set OPP50 (0.95V) for VDD core */
                sleep-sequence = /bits/ 8 <
                    0x02 0x2d 0x25 0x1f /* Set VDD2 to 0.95V */
                >;

                /* Set OPP100 (1.10V) for VDD core */
                wake-sequence = /bits/ 8 <
                    0x02 0x2d 0x25 0x2b /* Set VDD2 to 1.1V */
                >;

                tps: tps@2d {
                    reg = <0x2d>;
                };
                rtc@68 {
                    compatible = "maxim,ds1388";
                    reg = <0x68>;
                };
            };
            
            elm: elm@48080000 {
                status = "okay";
            };

            gpmc: gpmc@50000000 {
                status = "okay";
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&nandflash_pins_default>;
                pinctrl-1 = <&nandflash_pins_sleep>;
                ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
                nand@0,0 {
                    reg = <0 0 0>; /* CS0, offset 0 */
                    nand-bus-width = <8>;
                    gpmc,device-width = <1>;
                    gpmc,sync-clk-ps = <0>;
                    gpmc,cs-on-ns = <0>;
                    gpmc,cs-rd-off-ns = <44>;
                    gpmc,cs-wr-off-ns = <44>;
                    gpmc,adv-on-ns = <6>;
                    gpmc,adv-rd-off-ns = <34>;
                    gpmc,adv-wr-off-ns = <44>;
                    gpmc,we-on-ns = <0>;
                    gpmc,we-off-ns = <40>;
                    gpmc,oe-on-ns = <0>;
                    gpmc,oe-off-ns = <54>;
                    gpmc,access-ns = <64>;
                    gpmc,rd-cycle-ns = <82>;
                    gpmc,wr-cycle-ns = <82>;
                    gpmc,wait-on-read = "true";
                    gpmc,wait-on-write = "true";
                    gpmc,bus-turnaround-ns = <0>;
                    gpmc,cycle2cycle-delay-ns = <0>;
                    gpmc,clk-activation-ns = <0>;
                    gpmc,wait-monitoring-ns = <0>;
                    gpmc,wr-access-ns = <40>;
                    gpmc,wr-data-mux-bus-ns = <0>;
                    ti,nand-ecc-opt= "bch8";
                    ti,elm-id = <&elm>;
                    /* MTD partition table */
                            /* All SPL-* partitions are sized to minimal length
                     * which can be independently programmable. For
                     * NAND flash this is equal to size of erase-block */
                    #address-cells = <1>;
                    #size-cells = <1>;
                        partition@0 {
                        label = "NAND.SPL";
                        reg = <0x00000000 0x00020000>;
                    };
                    partition@1 {
                        label = "NAND.SPL.backup1";
                        reg = <0x00020000 0x00020000>;
                    };
                    partition@2 {
                        label = "NAND.SPL.backup2";
                        reg = <0x00040000 0x00020000>;
                    };
                    partition@3 {
                        label = "NAND.SPL.backup3";
                        reg = <0x00060000 0x00020000>;
                    };
                    partition@4 {
                        label = "NAND.u-boot";
                        reg = <0x00080000 0x00100000>;
                    };
                    partition@5 {
                        label = "NAND.u-boot-env";
                        reg = <0x00180000 0x00020000>;
                    };
                    partition@6 {
                        label = "NAND.kernel";
                        reg = <0x001A0000 0x00800000>;
                    };
                    partition@7 {
                        label = "NAND.dtb";
                        reg = <0x009A0000 0x00020000>;
                    };
                    partition@8 {
                        label = "NAND.bkfs";
                        reg = <0x009C0000 0x00A00000>;
                    };
                    partition@9 {
                        label = "NAND.file-system";
                        reg = <0x013C0000 0x0EC40000>;
                    };
                };
            };
            musb: usb@47400000 {
                status = "okay";

                control@44e10000 {
                    status = "okay";
                };

                usb-phy@47401300 {
                    status = "okay";
                };

                usb-phy@47401b00 {
                    status = "okay";
                };

                usb@47401000 {
                    status = "okay";
                };

                usb@47401800 {
                    status = "okay";
                    dr_mode = "host";
                };

                dma-controller@07402000  {
                    status = "okay";
                };
            };

        };

        vbat: fixedregulator@0 {
            compatible = "regulator-fixed";
            regulator-name = "vbat";
            regulator-min-microvolt = <5000000>;
            regulator-max-microvolt = <5000000>;
            regulator-boot-on;
        };

        lis3_reg: fixedregulator@1 {
            compatible = "regulator-fixed";
            regulator-name = "lis3_reg";
            regulator-boot-on;
        };

    };




    #include "tps65910.dtsi"

    &tps {
        vcc1-supply = <&vbat>;
        vcc2-supply = <&vbat>;
        vcc3-supply = <&vbat>;
        vcc4-supply = <&vbat>;
        vcc5-supply = <&vbat>;
        vcc6-supply = <&vbat>;
        vcc7-supply = <&vbat>;
        vccio-supply = <&vbat>;

        regulators {
            vio_reg: regulator@1 {
                regulator-always-on;
            };

            vdd1_reg: regulator@2 {
                /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
                regulator-name = "vdd_mpu";
                regulator-min-microvolt = <912500>;
                regulator-max-microvolt = <1378000>;
                regulator-boot-on;
                regulator-always-on;
            };

            vdd2_reg: regulator@3 {
                /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
                regulator-name = "vdd_core";
                regulator-min-microvolt = <912500>;
                regulator-max-microvolt = <1150000>;
                regulator-boot-on;
                regulator-always-on;
            };

            vdd3_reg: regulator@4 {
                regulator-always-on;
            };

            vdig1_reg: regulator@5 {
                regulator-always-on;
            };

            vdig2_reg: regulator@6 {
                regulator-always-on;
            };

            vpll_reg: regulator@7 {
                regulator-always-on;
            };

            vdac_reg: regulator@8 {
                regulator-always-on;
            };

            vaux1_reg: regulator@9 {
                regulator-always-on;
            };

            vaux2_reg: regulator@10 {
                regulator-always-on;
            };

            vaux33_reg: regulator@11 {
                regulator-always-on;
            };

            vmmc_reg: regulator@12 {
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
            };
        };
    };

    &mac {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
        dual_emac;
    };

    &davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
    };

    &cpsw_emac0 {
        phy_id = <&davinci_mdio>, <2>;
        phy-mode = "rgmii-txid";
    };

    &cpsw_emac1 {
        phy_id = <&davinci_mdio>, <3>;
        phy-mode = "rgmii-txid";
    };

    &gpio0 {
          ti,no-reset;
    };
    /*
    &gpio1 {
          ti,no-reset;
    };
    &gpio3 {
          ti,no-reset;
    };*/

    &gpio2 {
          ti,no-reset;
    };

    &gpio1 {
        pinctrl-names = "default";
        pinctrl-0 = <&gpio1_pins>;
        status = "okay";

    };

    &gpio3 {
            pinctrl-names = "default";
            pinctrl-0 = <&gpio3_pins>;
            status = "okay";
    };

    &spi1 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&spi1_pins>;
    };

    &i2c1 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&i2c1_pins>;
    };

    &i2c2 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&i2c2_pins>;
    };

    &dcan1 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&dcan1_pins>;
    };

  • This is the dts file which I am using. I have highlighted the section's which were added for changing pinmux mode of gpio1_28, gpio3_18 etc.

  • Move the pinctrl-0 = <&gpio1_pins>; and pinctrl-0 = <&gpio3_pins>; to:

      am33xx_pinmux: pinmux@44e10800 {
            pinctrl-names = "default";
            pinctrl-0 = <&gpio1_pins &gpio3_pins>;

    and everything will work as you expected.

  • Hi Kemal,

    Sorry for the delayed response. It worked after doing the suggested change in dts file. Now I'm able to control these gpio's through sysfs interface without any changes in uboot. Thank you so much !!

    But I didn't understand what was wrong with the dts file I was using, since I was able to control gpio pins gpio3_20, gpio3_13 other than gpio1_28 pin. I was following this thread. Also, pinmux details reflect our change i.e mode changed to 0x00000037. (cat pins (sys/kernel/debug/pinctrl/44e10878.pinmux)) for gpio1_28.

    Can you please help me in understanding the issue ?

    Thanks Again.

  • When the pin is not pinmuxed properly, it remains in unclear stage, sometimes this unclear stage may match your desired pinmux and the things work, but sometimes they do not match as you see in the case of gpio1_28.