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TMS320C6678: Ethernet boot mode, Boot Table Frame Payload format

Part Number: TMS320C6678

Hi, 

Can you please explain to me what is the format of the Boot Table Frame Payload, I am sending the boot table as .hex file directly after the boot table frame header in the ether boot packet as explained in the KeyStone Architecture - DSP Bootloader User Guide, but the DSP keeps sending boot requests, i am new to the DSP boot-loading, and its been quite some time since i worked with internet protocols, specially bootstrap protocol.

Please help 

  • Hi,

    We're looking into this.

    Best Regards,
    Yordan
  • Hi,

    More details to what we've done:

    1. setup

    So we're trying Ethernet boot, we set the switches on the DSP :
    (SW3,SW4,SW5,SW6,SW9) = 0101 1110 1100 0111 01 

    Started up the DSP and received the boot request, identical to the boot request detailed in the user guide.

    We use custom code to build the Ethernet packet, packet format identical to the Ethernet ready announcement format.

    Using 1200 bytes payload size, Ipv4\udp length fields are 1232 and 1212 (No errors shown in packet using Wireshark)

    BootTable frame Header ===> boot magic number = 0x544b, Opcode = 0x01

    Boot Table frame payload : chunks of the boot image created using the steps below

    Note: using ports 67 as des. and 68 as source makes the payload behave as a boot request, which shows errors in the wireshark capture

    2.Boot Image

    Used an example code from CCS ==> New CCS Project ==> Generic C66xx Device, example : SYS/BIOS Typical

    Built the project, copied .out file and .map file to utility folder

    command line

    call hex6x.exe app.rmd
    call b2ccs.exe app.btbl app.ccs
    call ccs2bin.exe app.ccs app.hex

    .rmd file:

    app.out
    --ascii
    --image
    --map=app.map
    --entrypoint _c_int00
    -order L

    ROMS
    {
    ROM1: org=0x00800000, len=0x20000, romwidth=32, memwidth=32 files={app.btbl} }

    got the .hex file

    3.loading the boot image

    In the software we divided this hex file into chunks of 1200 bytes,

    added to the end of the boot packet and sent each packet with a sequence number starting at 0(100 ms delay between), copied to the frame as it is after slicing to payload size

    added 1 more packet with 0 bytes payload size (did not add any bytes at the end of the frame) the total length of this packet is 46 bytes, normal packet length is 1246 except for the last packet which has shorter payload but is still a multiply of 4 bytes.

    Tried this and failed, tried with a different .hex with different .rmd file (minus the Rom1 option and with -boot option) also failed.

    4. we also used your example pcsendpkt.exe to send simple.eth that comes with the same example - also nothing happens and not working

    Questions:

    1. Do You have any cookbook for an Ethernet boot example that details the entire process for the C6778evm and works?
    2. what are the tools needed to build a bootable image that can be sent by the software we created? detailed build process if possible.

  • ***Update***
    We understood that a .eth boot file is needed for Ethernet boot, we tried using the platform_util_test program(used only the led util test), created .eth image file using hex6x, bconvert64x and bootpacket, tried sending the .eth file using custom code through Ethernet, the DSP stopped sending boot requests but nothing happens to the Leds, .rmd file is :

    app.out
    -a
    -boot
    -e _c_int00
    -order L

    ROMS
    {
    ROM1: org = 0x0080, length = 0x20000, memwidth = 32, romwidth = 32
    files = { app.btbl }

    }


    leds work with direct CCS debug. but not when sent with pcsendpkt.exe

    debuging the card after the boot process gives this error :

    Device core was hung. The debugger has forced the device to a ready state and recovered debug control, but your application's state is now corrupt. 


    Any ideas why is this happening?

  • Jameel,

    The ideal way to start with testing ethernet boot on this device is to run the Ethernet boot example that we provide in our software offering.
    processors.wiki.ti.com/.../Processor_SDK_RTOS_BOOT_C66x

    The Readme and the Software developer guide combined provide the boot tools and the description of how to set this up using TI EVM. Once you have the baseline Ethernet boot working, we can help you provide further guidance on booting your application.

    Please review the current Ethernet boot example that is provided at
    [SDK Install Path]/pdk_<platform>_<version>/packages/ti/boot/examples/ethernet/simple


    Regards,
    Rahul

    the SDK can be downloaded here:
    www.ti.com/.../PROCESSOR-SDK-C667X
  • Thank you for the reply, we managed to ethernet boot the keystone using the utility test example provided in the SDK package, I will leave here the steps we took to build the image, with a different app for each core :

    1. Create the source code in CCS
    2. Create the out files
    3. Copy out files to a new directory
    4. Also Copy to this directory these utilities that can be found in the ti directory:
    • Hex6x.exe
    • Mergebtbl.exe
    • Bconvert64x.exe
    • Bootpacket.exe
    • Create .rmd file for each out file, an example for core0 using L2 memory, inside the rmd we would include :

    core0.out

    -a

    -boot

    -e _c_int00

    -order L

     

    ROMS

    {

       ROM1: org = 0x10800000 , length = 0x00080000, memwidth = 32, romwidth = 32

             files = { core0.btbl }    

    }        

     

             We used global memory addresses : 0x10800000 , 0x11800000, …, 0x17800000

     

    1. Use mergebtbl.exe to merge them together into one single boot table.
    2. Use bconvert64.exe ,
    3. Use bootpacket.exe to slice the boot table into packets to be sent to the DSP
    4. Send the packets to the dsp through ethernet using the pcsendpkt.exe (we used a custom app for this but works the same)

     

    Commands for this example:

    hex6x app0.rmd

    hex6x app1.rmd

    hex6x app2.rmd

    hex6x app3.rmd

    hex6x app4.rmd

    hex6x app5.rmd

    hex6x app6.rmd

    hex6x app7.rmd

    mergebtbl core0.btbl core1.btbl core2.btbl core3.btbl core4.btbl core5.btbl core6.btbl core7.btbl app.btbl

    bconvert64x -le app.btbl app.le.btbl

    bootpacket app.le.btbl app.eth

     

     

    ***We managed to flash the leds from core0 but not from the other cores, although the other cores were able to write on their own L2 memory, any idea why is this happening ?

     

     

     

     

  • Did you populate the Magic address for each of the slave cores and issue an IPC interrupt for them to start executing.

    If you have not then you can refer to the slave core wakeup sequence here:

    examples/srio/srioboot_helloworld/src/srioboot_helloworld.c

     i recommend that you use global L2 address when populating the MAGIC Address.

    Regards,

    Rahul

  • I did, they do wake up and execute the code, but for some reason they don't control the leds, they write on their memory though, and yes i used global L2 addresses in the magic address population process, by the way, the magic addresses that i used come from each project map file is that ok ? like i generate all the out files and the .map files and check the address of each __c_init00 address, is that correct ?
  • Yes, generating the .out and then using the _c_init00 from the map file is the correct approach. Are all of the cores trying to access the same LED.
    Curious to know, how are the cores toggling the LED, is there a GPIO connected to the user LED or are you using the I2C command to FPGA to control the LED toggle as implemented on the EVM. Make sure all cores don`t try to send command or access the same LED at the same time by adding some kind of synchronization between the cores like a memory semaphore.

    Regards
    Rahul
  • Hi Rahul, 

    Thank you for the support, i think the problem is with the led toggle approach as you said and we will try to do it differently

    Best regards

    Jameel