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EVMK2H: Question related to use of BMC to select boot mode configuration

Part Number: EVMK2H

I have been able to successfully use the BMC program in NO-Boot mode on my evmK2H board to select a SPI BOOT configuration over SPI port 2 (which has an appropriate slave device connected). 

In reviewing the various bootmode entries in the BMC program, I noticed that  the entries listed in response to a >bootmode all command showed the following:

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 2 0x0000000000112005  ARM SPI

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12 0x0000000020112005  ARM SPI 10MHz

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My question is if it is possible to actually change the SPI master clock frequency by changing some of the upper bits in the bootmode configuration words?

The two configurations only differ by the 2 in the upper part of the configuration words, but can't find any documentation that explains what that '2' is actually doing to the boot procedure since it is higher than bit 15 and as I mentioned I haven't been able to find documentation that explains what bits above 15 (i.e. 63 downto 16) are actually being used for during boot up. Can you explain or point me to the suitable documentation?

Thanks!

  • Hi,

    Have a look at the following wiki:
    processors.wiki.ti.com/.../EVMK2H_Hardware_Setup

    Unfortunately bits above bit 25 are reserved and there is no publicly available explanation for them.

    Hope this helps.

    Best Regards,
    Yordan
  • Hello Yordan,

    So I would like to be able to follow a two stage boot process where first the Boot Parameter Table is overwritten with updated clock frequencies to speed up the SPI transfer data rate.

    Then once the clocks have been updated, transfer the actual application boot code via the spi running at the higher clock rate using ARM 0 as the boot master.  

    My question is if it is possible to simply set up the desired Boot Parameter Table in the SPI Nor flash memory using GP Header format where the first word is the length of the table, and the second word is the base address of the Boot Parameter table in memory and have the contents of that boot parameter table indicate a new address to load the user app from. Or is there some other way to perform a two stage boot with the intent of changing clock frequencies.

    The following image illustrates what I am trying to say:

    Or is there another way to accomplish this when booting on the ARM processor?

    Thanks!

    Richard

  • Richard,

    The BMC firmware spec is provided and maintained by the board manufacturer. The source and the documentation for which can be found here:

    http://www2.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx

    Click on Support and download for REV 1.0/REv1.1 and scroll down to the page as shown below:

    Only the DEVSTAT[16:0] are determined by the values in BMC bootmode setting. All other bits from 31:17 are used to drive other SOC pins as listed in the spec. [63:32] pins are not used or are reserved. For additional simplicity, you can refer to the table that I copied from a design spec they had provided :

    BitDevstat BitConfig Pin FunctionNormal Pin FunctionComments
    31 na na na reserved for wait in power off
    30 na na na reserved for wait in reset
    29 na na na reserved for other BMC SW config
    28 na na na reserved for other BMC SW config
    27       Reserved for future constant drive config bits
    26       Reserved for future constant drive config bits
    25   PACLKSEL PACLKSEL  
    24   CORECLKSEL CORECLKSEL  
    23       Reserved for future boot config latched values
    22   AVSIFSEL1 TIMI1 Reserved: EVM forces these bits to strap values during reset
    21   AVSIFSEL0 TIMI0 ""
    20   DDR3_REMAP_EN GPIO16  
    19   ARM_LENDIAN GPIO15 0 = little, 1 = is not supported; do in SW
    18   MAINPLLODSEL GPIO14  
    17   ARMAVSSHARED CORESEL3  

    Hope this helps.  Also, the values in the BMC boot table can be changed using instructions similar to the ones provided here:

    http://processors.wiki.ti.com/index.php/KeystoneII_Boot_Examples#Running_Ethernet_examples

    Refer: Fixing issue with BMC firmware and boot switches to boot ARM over ethernet on K2H EVM

    Regards,

    Rahul

  • Thanks Rahul,

    At this point, I'm pursuing a multistage boot approach to speed up the SPI transfer rate when performing a NOR SPI boot.