Hi,
I am looking for a code that does the following steps:
1. Init a buffer on the DDR with values running from 0 to 10000.
2. The embedded FPGA reads the buffer and makes a right-shift to the values.
3. FPGA sends the modified data to the DSP c6678 core 0 by Hyperlink.
4. Core 0 spreads the received data to the rest of cores (Core 1,Core 2,...,Core 7)
5. Each core applies a different and simple mathematical operation on the data and sends it at the end to a results buffer on the DDR.
Where may I find such an example or can you compose such an example?
THanks