RTOS/AM5728: EtherCAT Slave for DSP

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Hi,

This is an interesting topic. Can you share the background that you need to discard the verified ARM/PRUSS EtherCAT solution and choose DSP/PRUSS?

You may refer to the main_dsp.c under PDK packages\ti\drv\icss_emac\test\src , or NIMU_ICSS_BasicExample_idkAM572x_wSocLib_c66Exampleproject for the DSP/PRU interrupt mapping using CSL cross-bar function.

Below is the definition of DMB, DSB and MFENCE. It appears to be fine to use mfence in C66x replace DMB/DSB in ARM.
-------------------
DMB
Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction. It does not affect the ordering of any other instructions executing on the processor.

DSB
Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:
All explicit memory accesses before this instruction complete.
All Cache, Branch predictor and TLB maintenance operations before this instruction complete.

The MFENCE instruction from C66x will stall until the completion of all the CPU-triggered memory transactions, including:
• Cache line fills
• Writes from L1D to L2 or from CorePac to MSMC and/or other system
endpoints
• Victim write backs
• Block or global coherence operations
• Cache mode changes
• Outstanding XMC prefetch requests
------------------------

Regards,
Garrett

First of all Thx for your Help.

We want to run QNX on A15 later. On both DSP's one EtherCat Slave should run.

So my Job is to test if it is possible to run the slave full demo on the DSP.

I will explain Step by Step my problems in detail:

On my first try i was able to compile and run until calling PRUICSS_registerIrqHandler()
Even the ESC is started. Not so bad for a first try.

This PRUICSS_registerIrqHandler Routine is called 4 Times in bsp_start_esc_isr()
HOST_AL_EVENT evtOutNum=3 pruIsrNum=155
HOST_CMD_LOW_ACK_EVENT evtOutNum=4 pruIsrNum=156
HOST_SYNC0_EVENT evtOutNum=1 pruIsrNum=153
HOST_SYNC1_EVENT evtOutNum=2 pruIsrNum=154

Start Debug :
Set breakpoint on first call of PRUICSS_registerIrqHandler
Open C:\ti\bios_6_46_05_55\packages\ti\sysbios\family\c64p\HWI.c
set breakpoint in Hwi_Instance_init

if (intNum < 4 || intNum > 15) {
Error_raise(eb, Hwi_E_invalidIntNum, intNum, 0);
return (1);
}

=> IntNum = 155 => So I have a Problem cause IntNum > 15

Inspecting your mentioned example NIMU_ICSS_BasicExample_idkAM572x_wSocLib_c66Exampleproject I found follwing lines:


#ifdef _TMS320C6X
CSL_xbarDspIrqConfigure(1, CSL_XBAR_INST_DSP1_IRQ_76, CSL_XBAR_PRUSS2_IRQ_HOST8); /* link ISR */
CSL_xbarDspIrqConfigure(1, CSL_XBAR_INST_DSP1_IRQ_77, CSL_XBAR_PRUSS2_IRQ_HOST2); /* RX PKT ISR */
switchEmacCfg->linkIntNum=76;
switchEmacCfg->rxIntNum = 77;
#elif defined(__ARM_ARCH_7A__)
CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_120, CSL_XBAR_PRUSS2_IRQ_HOST8); /* link ISR */
CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_121, CSL_XBAR_PRUSS2_IRQ_HOST2); /* RX PKT ISR */
switchEmacCfg->linkIntNum=CSL_armGicGetGicIdForIrqInputLine(120);
switchEmacCfg->rxIntNum = CSL_armGicGetGicIdForIrqInputLine(121);


#ifdef _TMS320C6X
CSL_xbarDspIrqConfigure(1, CSL_XBAR_INST_DSP1_IRQ_89, CSL_XBAR_PRUSS2_IRQ_HOST9); /* link ISR */
CSL_xbarDspIrqConfigure(1, CSL_XBAR_INST_DSP1_IRQ_90, CSL_XBAR_PRUSS2_IRQ_HOST3); /* RX PKT ISR */
switchEmacCfg1->linkIntNum=89;
switchEmacCfg1->rxIntNum = 90;
#elif defined(__ARM_ARCH_7A__)
CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_122, CSL_XBAR_PRUSS2_IRQ_HOST9); /* link ISR */
CSL_xbarMpuIrqConfigure(CSL_XBAR_INST_MPU_IRQ_123, CSL_XBAR_PRUSS2_IRQ_HOST3); /* RX PKT ISR */
switchEmacCfg1->linkIntNum=CSL_armGicGetGicIdForIrqInputLine(122);
switchEmacCfg1->rxIntNum = CSL_armGicGetGicIdForIrqInputLine(123);
#endif

Here is a Mapping !! cool, It is important to know that the Number 120,121,122,123 are added with 32 => 152,153,154,155, ok nearly the same as in the full_demo

Here are my Questions!

The Interrupts which i have to map are still unclear. cause they must be under 16 as I shown.
The full demo uses 153..156 The example 152..155 . That makes it unclear to map even if the Numbers would be valid.

To be according to the ARM i wrote the Routine

void Board_xbarDspIrqConfigure(Uint32 dspInst, Uint32 irqNumIdx, CSL_XbarIrq xbarIrq)
{
CSL_xbarDspIrqConfigure(dspInst, irqNumIdx, xbarIrq);
}

Is this ok or should i delete the Core part like Board_xbarMpuIrqConfigure vs CSL_xbarMpuIrqConfigure (csl_device_xbar.c) does ??

Cause I want to run also later on DSP2. How can I automatically find out the DSP-Instance ??

Excuse for my new questions, but this part is not so easy to understand.


Ümit

Hi,

It seems you are missing the part of EventCombiner_dispatchPlug() and EventCombiner_enableEvent() in ICSS_EMAC_testInterruptInit() as shown in the test_common_utils.c in the NIMU_ICSS_BasicExample_idkAM572x_wSocLib_c66Exampleproject. Also, note the cfg file contains the

/*
* Enable Event Groups here and registering of ISR for specific GEM INTC is done
* using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
*/

Ecm.eventGroupHwiNum[0] = 6;
Ecm.eventGroupHwiNum[1] = 7;
Ecm.eventGroupHwiNum[2] = 8;
Ecm.eventGroupHwiNum[3] = 9;

The AM572x TRM (spruhz6i.pdf) Figure 5-5. DSP Subsystem Interrupt Management , should help understand the DSP interrupt mapping.
The xbar configuration maps the various interrupt sources to the device target INTC as shown in the figure, and eventually the interrupt output goes to C66x CPU Int[15:4]. The link may help as well: processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices

The CSL function CSL_chipReadDNUM() can be used to get core number - dsp instance.

Regards,
Garrett

Hi Garrett,

I have progarmmed the  part wirh EventCombiner().  The EscCmdLowAckIsr in now called().

After commenting out Board_getDigInput() in APPL_Application() (SPI_Transfer hangs, dont know why) i could find myEtherCat Slave in EC-Engineer via "Scan Ethernet Network"

On Starting "Diagnose Mode" on PC-EC-Enigineer  the Routine EcatIsr() is called on DSP Side like in ARM.

Problem:

Failure "Failed to chane master state: ERROR: Slave error (ErrCode 0x98110024)" and the "Motor Variables" are gone.

I will look deeper tomorrow.

Regards

Ümit

Hi;

Pressing on "DiagnoseMode"  in EC-Engieer

the ECATIsr() is called (I am sitting on the breakpoint) BUT

also following Message in EC-Engineer appears

The meaning is "Slave is not addressable".

Any Ideas ?

Regards

Ümit

The Problem is:

The VendorId in Ecat_def.h is only use in the ObjectRef 1018

On ARM the Slave is detected with VendorId 0x00000059 ObjectDictionary 1018=0x00000059
On DSP the Slave is detected with VendorId 0xE0000059 ObjectDictionary 1018=0x00000059

Where can I set the correct Identifier VendorId ??

After deleteing the ESI-Table on EC-Enginner i get following Information : 

DSP: VendorId: 0xe000059d ProductCode: 0x54490003 RevisionNor:0x1 

ARM:VendorId: 0x59d ProductCode: 0x54490003 RevisionNo:0x11

Found that .
It was my Failure. ECAT_LIMITED_DEMO was active,
Pardon

It's impressive that you can reach to this point! Is the demo fully working with DSP now?

Regards,

Garrett

Hi Garrett.

Currently I am in the Routine APPL_GeneratingMap() above main(). This routine i called on entering the "Diagnose Mode" on Ec-Engineer and calculates

Input/Output Size of the used PDO's. The calculation of the size in DSP is unfortunatly wrong! I find out the reason but i need a common solution :-)

The following line Fails on DSP calling it twice. (pPDOEntry is a *uint32_t)

OutputSize += (uint16_t)((*pPDOEntry) & 0xFF);

 

1st call  pPDOEntry Points to  &RxPDOMap.aEntry[0] and is a uint32_t

&RxPDOMap= 0x80039C5A is NOT32-Bit alligned  &RxPDOMap.aEntries[0].= 0x80039C5C  is 32-Bit alligned !!

2nd call  pPDOEntry Points to  &RxPDO1Map.aEntry[0]

&RxPDO1Map= 0x80039C70 is 32-Bit alligned  &RxPDO1Map.aEntries[0].= 0x80039C72  is NOT 32-Bit alligned !!

Cause I have a *uint32_t  and using a NOT alligend address it is no wonder to catch a wrong value via (*pPDOEntry)

Cause in EtherCat there i a lot of stuff belongs to the "CAN-ObjectRef" i fear the consequences. In other words: Fixing the Problem in this Routine is not a Problem but I need

a more common solution. 

Not using __attribute__((packed))  for STRUCT_PACKED_END  was not the solution.

May be Setting CONTROLLER_32BIT. Check this Monday.

 

 

Thx for your help.

Ümit

Hi Garret.
Good News!!

After Setting CONTROLLER_32BIT and Not using __attribute__((packed)) it runs!!
I can set the LED'S :-)

One last Question
How can I test the Sync0_Isr Sync1_Isr,

Thx for all.
I am happy

Hi,

Thanks for sharing this! 

Have you changed the ESC mode from freeRun to DC sync through master TwinCAT?

Regards, Garrett

Hi Garrett.

in ecat_def.h the DC_ Definition is defined as follows.

#define DC_SUPPORTED 1

Ümit

Hi,

Have you checked this old link - processors.wiki.ti.com/.../Running_AM335x_EtherCAT_Application_in_DC_Mode, to change operation mode to DC?

Regards,
Garrett

Thx Garret,

Even the ARM Slave does not run with DC. The Slave does not go in operational (stays in SafeOp).

Not sure. I have just setted Operation-Mode from FreeRun to DC-Synchron in Ec-Engineer.

I will check later the TwinCAT Settings in Detail. (Tasks and so on)

Currently i do not work on this issue.

Unfortunately I captured a new failure, which i for me now more important.

Starting DSP Application, enter Ec-Enginneer Diagnose-Mode. Set Led, all is ok.

The INDUSTRIAL LED0= is green.Master state Change from Init to Pre-Op to Safe-Op to Op: seems perfect!

Than I get cyclic "No Response on cyclic Ethernet Frame" every 3-10 Minutes as DBG-Information in Message-View.

Also The Processing Unit Error Counter increases every 10-20 seconds! (This can be ok; cause it is the same behaviour on ARM)

After 1 Hour  the connenction break down.

DBG | 2018-06-12 15:01:44 | Retry sending a acyclic frame due to frame loss
INF | 2018-06-12 15:01:44 | Slave with station address 1001 removed from network
DBG | 2018-06-12 15:01:44 | BusMismatch: wPrevFixedAddress=0, wPrevAIncAddress=0x0001, wPrevPort=255, Bus=0x0/0x0/0x0, Cfg=0x59D/0x54490003/0x11
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | No response on cyclic Ethernet frame
DBG | 2018-06-12 15:01:44 | Retry sending a acyclic frame due to frame loss

Maybe following Definition is incorrect? (changed by patch)

-#define MIN_PD_CYCLE_TIME                         0x7A120
+#define MIN_PD_CYCLE_TIME                         0x79E0// 31.2us 0x7A120

I am not sure if I must set ESC_32BIT_ACCESS. If I do so the Programm does not compile.

ESC_DC_SYNC_ACTIVATION_OFFSET is not defined.

Ümit

In Routine CheckIfEcatError()  the WdStateOk (ESC_PD_WD_TRIGGER_MASK) is not setted so that Slave will Change to SafeOp.

 

HW_EscReadWord(WdStatusOK, ESC_PD_WD_STATE);

WdStatusOK = SWAPWORD(WdStatusOK);

if (!(WdStatusOK & ESC_PD_WD_TRIGGER_MASK) && (nPdOutputSize > 0))

{

/*The device is in OP state*/

if (bEcatOutputUpdateRunning

#if !OP_PD_REQUIRED

&& bEcatFirstOutputsReceived

#endif

)

{

AL_ControlInd(STATE_SAFEOP, ALSTATUSCODE_SMWATCHDOG);

return;

}

I have setted the Watchdog Directive to 0 so that the WD check is in the Subsystem.
=> ECAT_CheckWatchdog instead of ECT_CheckIfEcatError()

Here the WD-Counter will be greater 100 so that the Slave changes to SafeOp!

The WD-Counter is resetted on following the PDITask it must be called before WD-Counter increases 100.

The behaviour is unclear, cause in ARM-Subsystem this Watchdog overrun doesn't occur.

1)
I will check if the Slave runs when I increase the WD_Time(100) to greater value.

2) These Defineds in ecat_def.h are also unclear:

ESC_32BIT_ACCESS = 0 cause I can not compile
MIN_PD_CYCLE_TIME = 0x79E0 => don't know how to calculate
Ümit

Hi Ümit,

The PDI cycle time is calculated in PDI_Isr() from ecatappl.c:

#else //!TIESC_HW
/* In TI ESC above approach won't work to figure out cycle exceeded scenario as it may take longer
to clear AL event IRQ by firmware, so we measure PDI ISR period instead */

It basically log the time of PDI_Isr() using the API bsp_get_local_sys_time() which returns 64-bit local system time (nanosec resolution) using PRU IEP timer.

Regards,
Garrett

#define SUPPORT_TI_ESC_CYCLE_EXCEEDED_COUNTER 1 in ecat_def.h

Test with TwinCAT 3.1.

Set LED ok

running 3 days (incoming PDI's) let the Industrial LED blink!

Set LED ok

Regards,

Ümit

Hi Garret.

I have let it run for a day with following definitions.

#define UPPORT_TI_ESC_CYCLE_EXCEEDED_COUNTER 0

#define MIN_PD_CYCLE_TIME 0xFA00 // 64 ms

It seems to work

Regards

Ümit

Hi Garrett.

I have a question belong to TwinCAT3 EtherCat Simulation.

Have you a "TwinCat3 Simulation for your Sitara Example Slave"

My idea.

Ethercat Simulation with "ESI of your Example."
Connect with Ec-Enginner to the Simulator on same PC

Set LED on EC-Enginner-Master. see the LED-Value in TwinCAT3-Simulation
write back a Value => see that in Ec-Enginneer (PLC Programm?)

The Document TE1111_TC3_EtherCAT_Simulation_en.pdf helps until the Point What else needs to be done?

Cause i have not found an example or deeper documentation the follwing steps make Problems.

Ümit

Ümit,

let me find out if our team has tried the TwinCAT3 simulation, meanwhile, you may try to get help from ETG developer forum -www.ethercat.org/login.aspx

Do you mind to open a new thread as this simulation topic is not directly tied to 'EtherCAT Slave for DSP'?

Thanks,
Garrett