AM4372: LPDDR2 connections

Sergey Sinyakov

Part Number: AM4372
Other Parts Discussed in Thread: CODECOMPOSER

Hello. We use 16-bit lpddr2 module (IS43LD16640C-25) with am4372 processor.

To configure EMIF we use "AM43xx EMIF Tools".

Calculated register values was written into gel-function to init EMIF when connected to core in CCS.

But DDR2 not work properly. In "CCS: memory view" at 0x80000000 and 16 bit config i look random (RRRR) words and work (OK) words:

0x80000000: RRRR RRRR RRRR RRRR OK OK OK OK

0x80000010: RRRR RRRR RRRR RRRR OK OK OK OK

0x80000020: RRRR RRRR RRRR RRRR OK OK OK OK

0x80000040: RRRR RRRR RRRR RRRR OK OK OK OK

.....

(OK) words write and read successfull, (RRRR) word read random values after refresh memory view window.

It's look as fail every four low address in eight. What configurable EMIF parameters may have this result?

We already check logical connection (not physical) between processor and LPDDR2. We have 2 board and both with some fail.

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

Please check that your connections follow the guidelines from section 5.13.8.2.2 in the AM437x Datasheet Rev. D.

0 Sergey Sinyakov over 7 years ago in reply to Biser Gatchev-XID

Prodigy 130 points

We check connection. It's correspond to guidelines.

0 JJD over 7 years ago in reply to Sergey Sinyakov

TI__Guru* 85990 points

Can you double check that NARROW mode is set in SDRAM_CONFIG register, bit[15:14]=0x1

Thanks,

james

0 Sergey Sinyakov over 7 years ago in reply to JJD

Prodigy 130 points

James, I check SDRAM_CONFIG NARROW - it's 0x1 (16 bit).

0 Sergey Sinyakov over 7 years ago in reply to Biser Gatchev-XID

Prodigy 130 points

Thanks you to link. I check connection to LPDDR3. It's confirm to guide. But problem not disappeared.

Can you comments that "The EMIF always performs burst accesses to the SDRAM" In section 9.3.3.10 SPRUHL7G? Code Composer use that method when read memory through JTAG ?
May unconnected line DQS or another look as my problem?

Please, help me if you can. I'm losing hope.

0 JJD over 7 years ago in reply to Sergey Sinyakov

TI__Guru* 85990 points

Hi Sergey, don't give up hope! It seems like it is just a configuration issue since you are getting good results on half of the memory. Can you dump all of the DDR controller registers from CCS. That's 0x4c000000-0x4c00031c

Thanks,
James

0 Sergey Sinyakov over 7 years ago in reply to JJD

Prodigy 130 points

Thank you James!

There are registers from Code Composer View Memory at 0x4c000000 after initialize RAM GEL function run:

0x4C000000   EMIF_EMIF4D_MOD_ID_REV
0x4C000000   50440500
0x4C000004   EMIF_EMIF4D_STS
0x4C000004   40000004
0x4C000008   EMIF_EMIF4D_SDRAM_CONFIG
0x4C000008   80805232
0x4C00000C   EMIF_EMIF4D_SDRAM_CONFIG_2
0x4C00000C   00000000
0x4C000010   EMIF_EMIF4D_SDRAM_REFRESH_CTRL
0x4C000010   000000D4
0x4C000014   EMIF_EMIF4D_SDRAM_REFRESH_CTRL_SHADOW
0x4C000014   000000D4
0x4C000018   EMIF_EMIF4D_SDRAM_TIMING_1
0x4C000018   00000000
0x4C00001C   EMIF_EMIF4D_SDRAM_TIMING_1_SHADOW
0x4C00001C   00000000
0x4C000020   EMIF_EMIF4D_SDRAM_TIMING_2
0x4C000020   20260993
0x4C000024   EMIF_EMIF4D_SDRAM_TIMING_2_SHADOW
0x4C000024   20260993
0x4C000028   EMIF_EMIF4D_SDRAM_TIMING_3
0x4C000028   5F8C423F
0x4C00002C   EMIF_EMIF4D_SDRAM_TIMING_3_SHADOW
0x4C00002C   5F8C423F
0x4C000030   EMIF_EMIF4D_LPDDR2_NVM_TIMING
0x4C000030   00000000
0x4C000034   EMIF_EMIF4D_LPDDR2_NVM_TIMING_SHADOW
0x4C000034   00000000
0x4C000038   EMIF_EMIF4D_POWER_MANAGEMENT_CTRL
0x4C000038   00000000
0x4C00003C   EMIF_EMIF4D_POWER_MANAGEMENT_CTRL_SHADOW
0x4C00003C   00000000
0x4C000040   EMIF_EMIF4D_LPDDR2_MODE_REG_DATA
0x4C000040   00000000   00000000   00000000   00000000
0x4C000050   EMIF_EMIF4D_LPDDR2_MODE_REG_CONFIG
0x4C000050   40000002
0x4C000054   EMIF_EMIF4D_OCP_CONFIG
0x4C000054   07770000
0x4C000058   EMIF_EMIF4D_OCP_CONFIG_VALUE_1
0x4C000058   9000190A
0x4C00005C   EMIF_EMIF4D_OCP_CONFIG_VALUE_2
0x4C00005C   00042727
0x4C000060   EMIF_EMIF4D_IODFT_TEST_LOGIC_GLOBAL_CTRL
0x4C000060   00002011
0x4C000064   EMIF_EMIF4D_IODFT_TEST_LOGIC_CTRL_MISR_RESULT
0x4C000064   00000000
0x4C000068   EMIF_EMIF4D_IODFT_TEST_LOGIC_ADDR_MISR_RESULT
0x4C000068   00000000
0x4C00006C   EMIF_EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1
0x4C00006C   00000000
0x4C000070   EMIF_EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2
0x4C000070   00000000
0x4C000074   EMIF_EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3
0x4C000074   00000000   00000000   00000000
0x4C000080   EMIF_EMIF4D_PERFORMANCE_CTR_1
0x4C000080   00000000
0x4C000084   EMIF_EMIF4D_PERFORMANCE_CTR_2
0x4C000084   00000000
0x4C000088   EMIF_EMIF4D_PERFORMANCE_CTR_CONFIG
0x4C000088   00010000
0x4C00008C   EMIF_EMIF4D_PERFORMANCE_CTR_MASTER_REGION_SELECT
0x4C00008C   00000000
0x4C000090   EMIF_EMIF4D_PERFORMANCE_CTR_TIME
0x4C000090   78FF9C2A
0x4C000094   EMIF_EMIF4D_MISC_REG
0x4C000094   00000000
0x4C000098   EMIF_EMIF4D_DLL_CALIB_CTRL
0x4C000098   00090000
0x4C00009C   EMIF_EMIF4D_DLL_CALIB_CTRL_SHADOW
0x4C00009C   00090000
0x4C0000A0   EMIF_EMIF4D_END_OF_INTR
0x4C0000A0   00000000
0x4C0000A4   EMIF_EMIF4D_SYSTEM_OCP_INTR_RAW_STS
0x4C0000A4   00000000
0x4C0000A8   EMIF_EMIF4D_LOW_LAT_OCP_INTR_RAW_STS
0x4C0000A8   00000000
0x4C0000AC   EMIF_EMIF4D_SYSTEM_OCP_INTR_STS
0x4C0000AC   00000000
0x4C0000B0   EMIF_EMIF4D_LOW_LAT_OCP_INTR_STS
0x4C0000B0   00000000
0x4C0000B4   EMIF_EMIF4D_SYSTEM_OCP_INTR_EN_SET
0x4C0000B4   00000000
0x4C0000B8   EMIF_EMIF4D_LOW_LAT_OCP_INTR_EN_SET
0x4C0000B8   00000000
0x4C0000BC   EMIF_EMIF4D_SYSTEM_OCP_INTR_EN_CLR
0x4C0000BC   00000000
0x4C0000C0   EMIF_EMIF4D_LOW_LAT_OCP_INTR_EN_CLR
0x4C0000C0   00000000   00000000
0x4C0000C8   EMIF_EMIF4D_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG
0x4C0000C8   50074CB4
0x4C0000CC   EMIF_EMIF4D_TEMPERATURE_ALERT_CONFIG
0x4C0000CC   00000000
0x4C0000D0   EMIF_EMIF4D_OCP_ERROR_LOG
0x4C0000D0   00000000
0x4C0000D4   EMIF_EMIF4D_READ_WRITE_LEVELING_RAMP_WINDOW
0x4C0000D4   00000000
0x4C0000D8   EMIF_EMIF4D_READ_WRITE_LEVELING_RAMP_CTRL
0x4C0000D8   00000000
0x4C0000DC   EMIF_EMIF4D_READ_WRITE_LEVELING_CTRL
0x4C0000DC   00000000   00000000
0x4C0000E4   EMIF_EMIF4D_DDR_PHY_CTRL_1
0x4C0000E4   0E288005
0x4C0000E8   EMIF_EMIF4D_DDR_PHY_CTRL_1_SHADOW
0x4C0000E8   0E288005   00000000   00000000   00000000   00000000   00000000
0x4C000100   EMIF_EMIF4D_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING
0x4C000100   00000000
0x4C000104   EMIF_EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING
0x4C000104   00000000
0x4C000108   EMIF_EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING
0x4C000108   00000000   00000000
0x4C000110   EMIF_EMIF4D_ECC_CTRL_REG
0x4C000110   00000000
0x4C000114   EMIF_EMIF4D_ECC_ADDR_RANGE_1
0x4C000114   00000000
0x4C000118   EMIF_EMIF4D_ECC_ADDR_RANGE_2
0x4C000118   00000000   00000000
0x4C000120   EMIF_EMIF4D_READ_WRITE_EXECUTION_THR
0x4C000120   00000000
0x4C000124   EMIF_EMIF4D_COS_CONFIG
0x4C000124   00FFFFFF   00000000   00000000
0x4C000130   EMIF_EMIF4D_1B_ECC_ERR_CNT
0x4C000130   00000000
0x4C000134   EMIF_EMIF4D_1B_ECC_ERR_THRSH
0x4C000134   00000000
0x4C000138   EMIF_EMIF4D_1B_ECC_ERR_DIST_1
0x4C000138   00000000
0x4C00013C   EMIF_EMIF4D_1B_ECC_ERR_ADDR_LOG
0x4C00013C   00000000
0x4C000140   EMIF_EMIF4D_2B_ECC_ERR_ADDR_LOG
0x4C000140   00000000
0x4C000144   EMIF_EMIF4D_PHY_STS_1
0x4C000144   001AA1F3
0x4C000148   EMIF_EMIF4D_PHY_STS_2
0x4C000148   000359A4
0x4C00014C   EMIF_EMIF4D_PHY_STS_3
0x4C00014C   00000000
0x4C000150   EMIF_EMIF4D_PHY_STS_4
0x4C000150   00020000
0x4C000154   EMIF_EMIF4D_PHY_STS_5
0x4C000154   00000099
0x4C000158   EMIF_EMIF4D_PHY_STS_6
0x4C000158   00000924
0x4C00015C   EMIF_EMIF4D_PHY_STS_7
0x4C00015C   00000000
0x4C000160   EMIF_EMIF4D_PHY_STS_8
0x4C000160   00000000
0x4C000164   EMIF_EMIF4D_PHY_STS_9
0x4C000164   00000000
0x4C000168   EMIF_EMIF4D_PHY_STS_10
0x4C000168   00000000
0x4C00016C   EMIF_EMIF4D_PHY_STS_11
0x4C00016C   00000000
0x4C000170   EMIF_EMIF4D_PHY_STS_12
0x4C000170   07000700
0x4C000174   EMIF_EMIF4D_PHY_STS_13
0x4C000174   07000700
0x4C000178   EMIF_EMIF4D_PHY_STS_14
0x4C000178   07000700
0x4C00017C   EMIF_EMIF4D_PHY_STS_15
0x4C00017C   07000700
0x4C000180   EMIF_EMIF4D_PHY_STS_16
0x4C000180   00000000
0x4C000184   EMIF_EMIF4D_PHY_STS_17
0x4C000184   03F703F5
0x4C000188   EMIF_EMIF4D_PHY_STS_18
0x4C000188   025902EB
0x4C00018C   EMIF_EMIF4D_PHY_STS_19
0x4C00018C   03F803E6
0x4C000190   EMIF_EMIF4D_PHY_STS_20
0x4C000190   03F20149
0x4C000194   EMIF_EMIF4D_PHY_STS_21
0x4C000194   00000000
0x4C000198   EMIF_EMIF4D_PHY_STS_22
0x4C000198   03D703D5
0x4C00019C   EMIF_EMIF4D_PHY_STS_23
0x4C00019C   023902CB
0x4C0001A0   EMIF_EMIF4D_PHY_STS_24
0x4C0001A0   03F803E6
0x4C0001A4   EMIF_EMIF4D_PHY_STS_25
0x4C0001A4   03F20149
0x4C0001A8   EMIF_EMIF4D_PHY_STS_26
0x4C0001A8   00000000
0x4C0001AC   EMIF_EMIF4D_PHY_STS_27
0x4C0001AC   10300000
0x4C0001B0   EMIF_EMIF4D_PHY_STS_28
0x4C0001B0   00000000   00000000   00000000   00000000   00000000   00000000   00000000
0x4C0001CC   00000000   00000000   00000000   00000000   00000000   00000000   00000000
0x4C0001E8   00000000   00000000   00000000   00000000   00000000   00000000
0x4C000200   EMIF_EMIF4D_EXT_PHY_CTRL_1
0x4C000200   00000040
0x4C000204   EMIF_EMIF4D_EXT_PHY_CTRL_1_SHADOW
0x4C000204   00000040
0x4C000208   EMIF_EMIF4D_EXT_PHY_CTRL_2
0x4C000208   00000050
0x4C00020C   EMIF_EMIF4D_EXT_PHY_CTRL_2_SHADOW
0x4C00020C   00000050
0x4C000210   EMIF_EMIF4D_EXT_PHY_CTRL_3
0x4C000210   00000050
0x4C000214   EMIF_EMIF4D_EXT_PHY_CTRL_3_SHADOW
0x4C000214   00000050
0x4C000218   EMIF_EMIF4D_EXT_PHY_CTRL_4
0x4C000218   00000050
0x4C00021C   EMIF_EMIF4D_EXT_PHY_CTRL_4_SHADOW
0x4C00021C   00000000
0x4C000220   EMIF_EMIF4D_EXT_PHY_CTRL_5
0x4C000220   00000050
0x4C000224   EMIF_EMIF4D_EXT_PHY_CTRL_5_SHADOW
0x4C000224   00000050
0x4C000228   EMIF_EMIF4D_EXT_PHY_CTRL_6
0x4C000228   00000050
0x4C00022C   EMIF_EMIF4D_EXT_PHY_CTRL_6_SHADOW
0x4C00022C   00000050
0x4C000230   EMIF_EMIF4D_EXT_PHY_CTRL_7
0x4C000230   00000020
0x4C000234   EMIF_EMIF4D_EXT_PHY_CTRL_7_SHADOW
0x4C000234   00000020
0x4C000234   EMIF_EMIF4D_EXT_PHY_CTRL_7_SHADOW
0x4C000234   00000020
0x4C000238   EMIF_EMIF4D_EXT_PHY_CTRL_8
0x4C000238   00000020
0x4C00023C   EMIF_EMIF4D_EXT_PHY_CTRL_8_SHADOW
0x4C00023C   00000020
0x4C000240   EMIF_EMIF4D_EXT_PHY_CTRL_9
0x4C000240   00000020
0x4C000244   EMIF_EMIF4D_EXT_PHY_CTRL_9_SHADOW
0x4C000244   00000020
0x4C000248   EMIF_EMIF4D_EXT_PHY_CTRL_10
0x4C000248   00000020
0x4C00024C   EMIF_EMIF4D_EXT_PHY_CTRL_10_SHADOW
0x4C00024C   00000020
0x4C000250   EMIF_EMIF4D_EXT_PHY_CTRL_11
0x4C000250   00000020
0x4C000254   EMIF_EMIF4D_EXT_PHY_CTRL_11_SHADOW
0x4C000254   00400040
0x4C000258   EMIF_EMIF4D_EXT_PHY_CTRL_12
0x4C000258   00000020
0x4C00025C   EMIF_EMIF4D_EXT_PHY_CTRL_12_SHADOW
0x4C00025C   00000020
0x4C000260   EMIF_EMIF4D_EXT_PHY_CTRL_13
0x4C000260   00000020
0x4C000264   EMIF_EMIF4D_EXT_PHY_CTRL_13_SHADOW
0x4C000264   00000020
0x4C000268   EMIF_EMIF4D_EXT_PHY_CTRL_14
0x4C000268   00000020
0x4C00026C   EMIF_EMIF4D_EXT_PHY_CTRL_14_SHADOW
0x4C00026C   00000020
0x4C000270   EMIF_EMIF4D_EXT_PHY_CTRL_15
0x4C000270   00000020
0x4C000274   EMIF_EMIF4D_EXT_PHY_CTRL_15_SHADOW
0x4C000274   00000020
0x4C000278   EMIF_EMIF4D_EXT_PHY_CTRL_16
0x4C000278   00000020
0x4C00027C   EMIF_EMIF4D_EXT_PHY_CTRL_16_SHADOW
0x4C00027C   00000020
0x4C000280   EMIF_EMIF4D_EXT_PHY_CTRL_17
0x4C000280   00000000
0x4C000284   EMIF_EMIF4D_EXT_PHY_CTRL_17_SHADOW
0x4C000284   00000000
0x4C000288   EMIF_EMIF4D_EXT_PHY_CTRL_18
0x4C000288   00000000
0x4C00028C   EMIF_EMIF4D_EXT_PHY_CTRL_18_SHADOW
0x4C00028C   00000000
0x4C000290   EMIF_EMIF4D_EXT_PHY_CTRL_19
0x4C000290   00000000
0x4C000294   EMIF_EMIF4D_EXT_PHY_CTRL_19_SHADOW
0x4C000294   00000000
0x4C000298   EMIF_EMIF4D_EXT_PHY_CTRL_20
0x4C000298   00000000
0x4C00029C   EMIF_EMIF4D_EXT_PHY_CTRL_20_SHADOW
0x4C00029C   00000000
0x4C0002A0   EMIF_EMIF4D_EXT_PHY_CTRL_21
0x4C0002A0   00000000
0x4C0002A4   EMIF_EMIF4D_EXT_PHY_CTRL_21_SHADOW
0x4C0002A4   00000000
0x4C0002A8   EMIF_EMIF4D_EXT_PHY_CTRL_22
0x4C0002A8   00000000
0x4C0002AC   EMIF_EMIF4D_EXT_PHY_CTRL_22_SHADOW
0x4C0002AC   00000000
0x4C0002B0   EMIF_EMIF4D_EXT_PHY_CTRL_23
0x4C0002B0   00000000
0x4C0002B4   EMIF_EMIF4D_EXT_PHY_CTRL_23_SHADOW
0x4C0002B4   00000000
0x4C0002B8   EMIF_EMIF4D_EXT_PHY_CTRL_24
0x4C0002B8   40001000
0x4C0002BC   EMIF_EMIF4D_EXT_PHY_CTRL_24_SHADOW
0x4C0002BC   40001000
0x4C0002C0   EMIF_EMIF4D_EXT_PHY_CTRL_25
0x4C0002C0   08102040
0x4C0002C4   EMIF_EMIF4D_EXT_PHY_CTRL_25_SHADOW
0x4C0002C4   08102040
0x4C0002C8   EMIF_EMIF4D_EXT_PHY_CTRL_26
0x4C0002C8   00000000
0x4C0002CC   EMIF_EMIF4D_EXT_PHY_CTRL_26_SHADOW
0x4C0002CC   00000000
0x4C0002D0   EMIF_EMIF4D_EXT_PHY_CTRL_27
0x4C0002D0   00000000
0x4C0002D4   EMIF_EMIF4D_EXT_PHY_CTRL_27_SHADOW
0x4C0002D4   00000000
0x4C0002D8   EMIF_EMIF4D_EXT_PHY_CTRL_28
0x4C0002D8   00000000
0x4C0002DC   EMIF_EMIF4D_EXT_PHY_CTRL_28_SHADOW
0x4C0002DC   00000000
0x4C0002E0   EMIF_EMIF4D_EXT_PHY_CTRL_29
0x4C0002E0   00000000
0x4C0002E4   EMIF_EMIF4D_EXT_PHY_CTRL_29_SHADOW
0x4C0002E4   00000000
0x4C0002E8   EMIF_EMIF4D_EXT_PHY_CTRL_30
0x4C0002E8   00000000
0x4C0002EC   EMIF_EMIF4D_EXT_PHY_CTRL_30_SHADOW
0x4C0002EC   00000000
0x4C0002F0   EMIF_EMIF4D_EXT_PHY_CTRL_31
0x4C0002F0   00000000
0x4C0002F4   EMIF_EMIF4D_EXT_PHY_CTRL_31_SHADOW
0x4C0002F4   00000000
0x4C0002F8   EMIF_EMIF4D_EXT_PHY_CTRL_32
0x4C0002F8   00000000
0x4C0002FC   EMIF_EMIF4D_EXT_PHY_CTRL_32_SHADOW
0x4C0002FC   00000000
0x4C000300   EMIF_EMIF4D_EXT_PHY_CTRL_33
0x4C000300   00000000
0x4C000304   EMIF_EMIF4D_EXT_PHY_CTRL_33_SHADOW
0x4C000304   00000000
0x4C000308   EMIF_EMIF4D_EXT_PHY_CTRL_34
0x4C000308   00000000
0x4C00030C   EMIF_EMIF4D_EXT_PHY_CTRL_34_SHADOW
0x4C00030C   00000000
0x4C000310   EMIF_EMIF4D_EXT_PHY_CTRL_35
0x4C000310   00000000
0x4C000314   00000000
0x4C000318   EMIF_EMIF4D_EXT_PHY_CTRL_36
0x4C000318   00000077
0x4C00031C   EMIF_EMIF4D_EXT_PHY_CTRL_36_SHADOW
0x4C00031C   00000077

P.S.:

I modify standart script from TI : "\ti\ccsv8\ccs_base\emulation\boards\evmam437x\gel\AM437x_EMIFconfig_HWlvl.gel"

In function AM43xx_LPDDR2_config() i place next code:

hotmenu AM43xx_LPDDR2_config()
{
	
	unsigned int i, read_reg;

    EMIF_PRCM_CLK_ENABLE();
	GEL_TextOut("EMIF CLK enabled\n");

	VTP_Enable();
	GEL_TextOut("VTP controller enabled\n");
    
	GEL_TextOut("Checking if DLL is ready...\n");
    WR_MEM_32(CM_DLL_CTRL, RD_MEM_32(CM_DLL_CTRL) & ~0x00000001 );
	//wait for DLL ready
	while((RD_MEM_32(CM_DLL_CTRL) & 0x4) == 0);
	GEL_TextOut("DLL is ready\n");
         
    GEL_TextOut("Configuring DDR IOs and Control Module registers...\n");
	
    GEL_TextOut("Starting RILI5 LPDDR2 configuration\n");
//THRESOLD BURST
    WR_MEM_32( 0x4C000120, 0x0);


//EMIF REGISTERS
    WR_MEM_32( 0x4C000018, 0xECA8C45A);
    WR_MEM_32( 0x4C00001C, 0xECA8C45A);
    WR_MEM_32( 0x4C000020, 0x20260993);
    WR_MEM_32( 0x4C000024, 0x20260993);
    WR_MEM_32( 0x4C000028, 0x5F8C423F);
    WR_MEM_32( 0x4C00002C, 0x5F8C423F);
    WR_MEM_32( 0x4C000008, 0x80805232);
    WR_MEM_32( 0x4C00000C, 0x0);
    WR_MEM_32( 0x4C000010, 0x000000D4);
    WR_MEM_32( 0x4C000014, 0x000000D4);
    WR_MEM_32( 0x4C0000C8, 0x50074CB4);
    WR_MEM_32( 0x4C0000CC, 0x0);
    WR_MEM_32( 0x4C0000D4, 0x0);
    WR_MEM_32( 0x4C0000D8, 0x0);
    WR_MEM_32( 0x4C0000DC, 0x0);
//DDR PHY CTRL REGISTER
    WR_MEM_32( 0x4C0000E4, 0x0E288005);
    WR_MEM_32( 0x4C0000E8, 0x0E288005);
    WR_MEM_32( 0x4C000200, 0x00000040);
    WR_MEM_32( 0x4C000204, 0x00000040);
    WR_MEM_32( 0x4C000208, 0x00000050);
    WR_MEM_32( 0x4C00020C, 0x00000050);
    WR_MEM_32( 0x4C000210, 0x00000050);
    WR_MEM_32( 0x4C000214, 0x00000050);
    WR_MEM_32( 0x4C000218, 0x00000050);
    WR_MEM_32( 0x4C000220, 0x00000050);
    WR_MEM_32( 0x4C000224, 0x00000050);
    WR_MEM_32( 0x4C000228, 0x00000050);
    WR_MEM_32( 0x4C00022C, 0x00000050);
    WR_MEM_32( 0x4C000230, 0x00000020);
    WR_MEM_32( 0x4C000234, 0x00000020);
    WR_MEM_32( 0x4C000238, 0x00000020);
    WR_MEM_32( 0x4C00023C, 0x00000020);
    WR_MEM_32( 0x4C000240, 0x00000020);
    WR_MEM_32( 0x4C000244, 0x00000020);
    WR_MEM_32( 0x4C000248, 0x00000020);
    WR_MEM_32( 0x4C00024C, 0x00000020);
    WR_MEM_32( 0x4C000250, 0x00000020);
    WR_MEM_32( 0x4C000258, 0x00000020);
    WR_MEM_32( 0x4C00025C, 0x00000020);
    WR_MEM_32( 0x4C000260, 0x00000020);
    WR_MEM_32( 0x4C000264, 0x00000020);
    WR_MEM_32( 0x4C000268, 0x00000020);
    WR_MEM_32( 0x4C00026C, 0x00000020);
    WR_MEM_32( 0x4C000270, 0x00000020);
    WR_MEM_32( 0x4C000274, 0x00000020);
    WR_MEM_32( 0x4C000278, 0x00000020);
    WR_MEM_32( 0x4C00027C, 0x00000020);
    WR_MEM_32( 0x4C000280, 0x00000000);
    WR_MEM_32( 0x4C000284, 0x00000000);
    WR_MEM_32( 0x4C000288, 0x00000000);
    WR_MEM_32( 0x4C00028C, 0x00000000);
    WR_MEM_32( 0x4C000290, 0x00000000);
    WR_MEM_32( 0x4C000294, 0x00000000);
    WR_MEM_32( 0x4C000298, 0x00000000);
    WR_MEM_32( 0x4C00029C, 0x00000000);
    WR_MEM_32( 0x4C0002A0, 0x00000000);
    WR_MEM_32( 0x4C0002A4, 0x00000000);
    WR_MEM_32( 0x4C0002A8, 0x00000000);
    WR_MEM_32( 0x4C0002AC, 0x00000000);
    WR_MEM_32( 0x4C0002B0, 0x00000000);
    WR_MEM_32( 0x4C0002B4, 0x00000000);
    WR_MEM_32( 0x4C0002B8, 0x40001000);
    WR_MEM_32( 0x4C0002BC, 0x40001000);
    WR_MEM_32( 0x4C0002C0, 0x08102040);
    WR_MEM_32( 0x4C0002C4, 0x08102040);
    WR_MEM_32( 0x4C0002C8, 0x00000000);
    WR_MEM_32( 0x4C0002CC, 0x00000000);
    WR_MEM_32( 0x4C0002D0, 0x00000000);
    WR_MEM_32( 0x4C0002D4, 0x00000000);
    WR_MEM_32( 0x4C0002D8, 0x00000000);
    WR_MEM_32( 0x4C0002DC, 0x00000000);
    WR_MEM_32( 0x4C0002E0, 0x00000000);
    WR_MEM_32( 0x4C0002E4, 0x00000000);
    WR_MEM_32( 0x4C0002E8, 0x00000000);
    WR_MEM_32( 0x4C0002EC, 0x00000000);
    WR_MEM_32( 0x4C0002F0, 0x00000000);
    WR_MEM_32( 0x4C0002F4, 0x00000000);
    WR_MEM_32( 0x4C0002F8, 0x00000000);
    WR_MEM_32( 0x4C0002FC, 0x00000000);
    WR_MEM_32( 0x4C000300, 0x00000000);
    WR_MEM_32( 0x4C000304, 0x00000000);
    WR_MEM_32( 0x4C000308, 0x00000000);
    WR_MEM_32( 0x4C00030C, 0x00000000);
    WR_MEM_32( 0x4C000310, 0x00000000);
    WR_MEM_32( 0x4C000314, 0x00000000);
    WR_MEM_32( 0x4C000418, 0x00000000);
    WR_MEM_32( 0x4C00041C, 0x00000000);
//IO CONTROL REGISTERS
    WR_MEM_32( 0x44E1131C, 0x00000003);
    WR_MEM_32( 0x44E11404, 0x00000084);
    WR_MEM_32( 0x44E11408, 0x00000000);
    WR_MEM_32( 0x44E1140C, 0x00000000);
    WR_MEM_32( 0x44E11440, 0x20000084);
    WR_MEM_32( 0x44E11444, 0x20000084);
    WR_MEM_32( 0x44E11448, 0x20000084);
    WR_MEM_32( 0x44E1144C, 0x20000084);
    WR_MEM_32( 0x44E11460, 0x00020101);
//LLPDDR2 MODE REGISTERS
    WR_MEM_32( 0x4C000050, 0x0000000A);
    WR_MEM_32( 0x4C000040, 0x00000056);
//nr
//nr
    WR_MEM_32( 0x4C000050, 0x00000001);
    WR_MEM_32( 0x4C000040, 0x00000043);
//nr
//nr
    WR_MEM_32( 0x4C000050, 0x00000002);
    WR_MEM_32( 0x4C000040, 0x00000002);
//nr
//nr
    WR_MEM_32( 0x4C000050, 0x40000002);
    WR_MEM_32( 0x4C000040, 0x00000002);
//nr
//nr

}

My AM437xx_GP_EVM_Initialization():

hotmenu AM43xx_GP_EVM_Initialization()
    {
    GEL_TextOut("**** AM437x GP EVM Initialization is in progress .......... \n","Output",1,1,1);
    ARM_OPP100_Config(1); //1=GP EVM with LDDR2
    Enable_VTT_Regulator();
    AM43xx_LPDDR2_config();

    GEL_TextOut("Turning on EDMA... \n");
    EdmaPrcm();
    GEL_TextOut("EDMA is turned on... \n");

    GEL_TextOut("**** AM437x GP EVM Initialization is Done ****************** \n\n\n","Output",1,1,1);
    }

0 JJD over 7 years ago in reply to Sergey Sinyakov

TI__Guru* 85990 points

Hi Sergey, in your GEL, you need to follow a little bit of the sequence of the original GEL for proper DDR initialization. After write to all of the registers in the EMIF and PHY, you need to follow the sequence below to ensure the memory gets initialized properly and that you wait until the LPDDR2 has completed its initialization:

//finished with EMIF config

//set init bit back to enable

WR_MEM_32(EMIF_SDRAM_REF_CTRL,0x3000);

//this write initiates and EMIF initialization and also latches values to PHY

WR_MEM_32(EMIF_SDRAM_CONFIG,LPDDR2_SDRAM_CONFIG);

WR_MEM_32(EMIF_SDRAM_REF_CTRL,LPDDR2_REF_CTRL);

WR_MEM_32(EMIF_SDRAM_REF_CTRL_SHDW,LPDDR2_REF_CTRL);

GEL_TextOut("\n\nEMIF configuration is complete\n",,,,,i);

//at this point, we can check the MR0 register of the LPDDR2 memory to ensure auto-initialization in memory is complete

//when complete, DAI should be 0x0, RZQI should be 0x3

//check memory datasheet for definition of these bits

GEL_TextOut("Waiting for LPDDR2 autoinitialization to be ready...\n");

GEL_TextOut("\n");

WR_MEM_32(EMIF_LPDDR2_MODE_REG_CFG,0x00000000);

while((RD_MEM_32(EMIF_LPDDR2_MODE_REG_DATA) & 0xFF) != 0x18);

GEL_TextOut("LPDDR2 autoinitialization complete!\n");

Then you can write the LPDDR2 mode registers to complete the init.

Also, did you perform any bit swapping when laying out the board traces?

Regards,

James

0 Sergey Sinyakov over 7 years ago in reply to JJD

Prodigy 130 points

Thank you James.

1. I check connection to LPDDR2 - there are no swapping in data lines on board traces.

2. I see this code in original gel file.

Now I add this code to my sequence before write mode registers. Script print "LPDDR2 autoinitialization complete!\" in console.

But no visible changes in memory view window.

When I add this, I use my values for LPDDR2_SDRAM_CONFIG = 0x80805232, LPDDR2_REF_CTRL = 0x0000081A.

I try to read LDPPR MODE REGISTER at 0x5 - manufactured ID - it is 0x1B, what correspond to datasheet.

I remind you:

- First four words in memory view at address 0x80000000 read 0x6CFE, 0xFFA1, 0XFFE6, 0X4CFC. Next read values after refresh 0x6CFF, 0xFFA1, 0xFFE6, 0x4EFC. And next read values in values changes some bits.

- If I write throught Code Composer Memory View values 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, then next read values 0x7FFF, 0xFFFF, 0xFFFF, 0x7FFF. after refresh sometimes first values have 0xFFFF, sometimes 0x7FFF. next 3 values no changes.

Words at address 0x80000008 - 0x8000000F read and write successful.

And next address situation repeated. Four words read random values, four words read and write successful, four words read random....

0 JJD over 7 years ago in reply to Sergey Sinyakov

TI__Guru* 85990 points

With that new information, it looks like a timing issue. Furthermore, if i look back at the register dump you provided, it looks like one of your timing register did not get written properly

0x4C000010 EMIF_EMIF4D_SDRAM_REFRESH_CTRL

0x4C000010 000000D4

0x4C000014 EMIF_EMIF4D_SDRAM_REFRESH_CTRL_SHADOW

0x4C000014 000000D4

0x4C000018 EMIF_EMIF4D_SDRAM_TIMING_1

0x4C000018 00000000

Also, the refresh control register doesn't look correct based on the speed you should be running the DDR (266MHz)

I used the datasheet of the memory vendor you provided, and filled out the EMIF tool spreadsheet. There are several discrepancies which i found. Try using the results that i got in the attached spreadsheet, and once you have plugged those into the GEL, ensure a data dump of the registers reflects those values.

If you have questions on the spreadsheet results, let me know.

Regards,

James

e2epost_SPRAC70_AM437x_EMIF_Configuration_Tool_V20.xlsx

0 Sergey Sinyakov over 7 years ago in reply to JJD

Prodigy 130 points

Thank you very much James!!!!

Your remark about zero value of EMIF_EMIF4D_SDRAM_TIMING_1 is a key to resolve my problem.

It's amazing, but GEL-script write to EMIF_EMIF4D_SDRAM_TIMING_1 ignored by CCS or hardware and EMIF_EMIF4D_SDRAM_TIMING_1 hold zero values.

I add next instruction at the end of Initialize script and Code Composer write register successful.

WR_MEM_32( 0x4C000018, 0xEA86B491);
WR_MEM_32( 0x4C00001C, 0xEA86B491);

After that my LPDDR2 work successful. I try to test RAM later, but this problem resolved.

Thank you.

P.S. If you have idea about strange CodeComposer logic or script sequence error please let me know.

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AM4372: LPDDR2 connections