AM3352: DDR3 software leveling

Nadav Yafe

Part Number: AM3352

Hi,

We are trying to do software leveling with AM3352 and DDR3L.

While using the Ratio Seed spreadsheet I found out that DQS1 lengths if longer than the CLK and DQS0 is shorter than CLK.

So on one case I need to invert the clock on "1" and on the second case I have keep it "0 ".

Parameters			Comments
DDR clock frequency	400	MHz	input maximum frequency you will use
PHY_INVERT_CLKOUT	0		If (DDR_CK length) < (DDR_DQS length), then use 1. If (DDR_CK length) > (DDR_DQS length), then use 0.

Trace Length (inches)
	Byte 0	Byte 1
DDR_CK trace	0.7906	0.7906	input the average of DDR_CK and DDR_CKn traces. If you have two x8 memories, use the trace lengths for each corresponding byte.
DDR_DQSx trace	0.727	0.9852	x can be 0 or 1, corresponding to each byte.

Intermediate values (per byte lane)
WR DQS	1	FFFFFFFFFD	these are just used for the calculations below
RD DQS	40	40	these are just used for the calculations below
RD DQS GATE	69	72	these are just used for the calculations below

How can we do software leveling in this layout?

Thanks,

Nadav

over 7 years ago

0 JJD over 7 years ago

TI__Guru* 80310 points

Nadav, just set INVERT_CLKOUT=1. This should work even in your case

Thanks,
James

0 Nadav Yafe over 7 years ago in reply to JJD

Prodigy 130 points

James,

we tried to run the script with the new radio seed while choosing invert.

it seems wrong because for some reason both DATA_PHY_RD_DQS_SLAVE_RATIO and DATA_PHY_WR_DQS_SLAVE_RATIO is 0.

we tried to use the optimum Value and as suspected it failed.

This is the log that I received

[CortxA8]

Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window

***************************************************************

The Slave Ratio Search Program Values are...

***************************************************************

PARAMETER MAX | MIN | OPTIMUM | RANGE

***************************************************************

DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000

DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x0e9 | 0x074 | 0xffffff17

DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000

DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f1 | 0x086 | 0x0bb | 0x06b

***************************************************************

rd_dqs_range = 0

fifo_we_range = 74

wr_dqs_range = 0

wr_data_range = bb

Optimal values not reached, rerunning program with new values...

***************************************************************

The Slave Ratio Search Program Values are...

***************************************************************

PARAMETER MAX | MIN | OPTIMUM | RANGE

***************************************************************

DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000

DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x0e9 | 0x074 | 0xffffff17

DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000

DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f1 | 0x086 | 0x0bb | 0x06b

***************************************************************

rd_dqs_range = 0

fifo_we_range = 0

wr_dqs_range = 0

wr_data_range = 0

Optimal values have been found!!

***************************************************************

The Slave Ratio Search Program Values are...

***************************************************************

PARAMETER MAX | MIN | OPTIMUM | RANGE

***************************************************************

DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000

DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x0e9 | 0x074 | 0xffffff17

DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000

DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f1 | 0x086 | 0x0bb | 0x06b

***************************************************************

===== END OF TEST =====

Ratio Seed values spreadsheet:

Parameters			Comments
DDR clock frequency	400	MHz	input maximum frequency you will use
PHY_INVERT_CLKOUT	1		If (DDR_CK length) < (DDR_DQS length), then use 1. If (DDR_CK length) > (DDR_DQS length), then use 0.

Trace Length (inches)
	Byte 0	Byte 1
DDR_CK trace	0.7906	0.7906	input the average of DDR_CK and DDR_CKn traces. If you have two x8 memories, use the trace lengths for each corresponding byte.
DDR_DQSx trace	0.727	0.9852	x can be 0 or 1, corresponding to each byte.

Intermediate values (per byte lane)
WR DQS	81	7C	these are just used for the calculations below
RD DQS	40	40	these are just used for the calculations below
RD DQS GATE	E9	F2	these are just used for the calculations below

Seed values used in CCS code
DATAx_PHY_RD DQS_SLAVE_RATIO	40
DATAx_PHY_FIFO_WE_SLAVE_RATIO	ED
DATAx_PHY_WR DQS_SLAVE_RATIO	7E

Register value
CMDx_PHY_CTRL_SLAVE_RATIO	100

0 JJD over 7 years ago in reply to Nadav Yafe

TI__Guru* 80310 points

Can you attach the GEL you are using when running the software leveling algorithm.

Thanks,
James

0 Nadav Yafe over 7 years ago in reply to JJD

Prodigy 130 points

Added GEL file.1425.AM3358_StarterKit.gel

0 JJD over 7 years ago in reply to Nadav Yafe

TI__Guru* 80310 points

Can you try running the leveling algorithm with the following changes in the GEL:

#define CMD_PHY_CTRL_SLAVE_RATIO 0x100

0 Nadav Yafe over 7 years ago in reply to JJD

Prodigy 130 points

Hi,
after changing the value mentioned above to 0x100 i ran the script again.

‎[CortxA8] ‎
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
‎1‎

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
‎40‎

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
ED

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS ‎Ratio Window
‎7E‎

‎***************************************************************‎
‎ The Slave Ratio Search Program Values are... ‎
‎***************************************************************‎
PARAMETER MAX | MIN | OPTIMUM | RANGE ‎
‎***************************************************************‎
DATA_PHY_RD_DQS_SLAVE_RATIO 0x041 | 0x03f | 0x040 | 0x002‎
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x0ec | 0x076 | 0xffffff14‎
DATA_PHY_WR_DQS_SLAVE_RATIO 0x07f | 0x07d | 0x07e | 0x002‎
DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f4 | 0x085 | 0x0bc | 0x06f‎
‎***************************************************************‎
rd_dqs_range = 40‎
fifo_we_range = 76‎
wr_dqs_range = 7e
wr_data_range = bc

Optimal values not reached, rerunning program with new values...‎

‎***************************************************************‎
‎ The Slave Ratio Search Program Values are... ‎
‎***************************************************************‎
PARAMETER MAX | MIN | OPTIMUM | RANGE ‎
‎***************************************************************‎
DATA_PHY_RD_DQS_SLAVE_RATIO 0x041 | 0x03f | 0x040 | 0x002‎
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x078 | 0x0ec | 0x0b2 | 0xffffff8c‎
DATA_PHY_WR_DQS_SLAVE_RATIO 0x085 | 0x07d | 0x081 | 0x008‎
DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f5 | 0x08a | 0x0bf | 0x06b‎
‎***************************************************************‎
rd_dqs_range = 0‎
fifo_we_range = 3c
wr_dqs_range = 3‎
wr_data_range = 3‎

Optimal values not reached, rerunning program with new values...‎

‎***************************************************************‎
‎ The Slave Ratio Search Program Values are... ‎
‎***************************************************************‎
PARAMETER MAX | MIN | OPTIMUM | RANGE ‎
‎***************************************************************‎
DATA_PHY_RD_DQS_SLAVE_RATIO 0x041 | 0x03f | 0x040 | 0x002‎
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x0b4 | 0x0b1 | 0x0b2 | 0x003‎
DATA_PHY_WR_DQS_SLAVE_RATIO 0x085 | 0x07f | 0x082 | 0x006‎
DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f2 | 0x08a | 0x0be | 0x068‎
‎***************************************************************‎
rd_dqs_range = 0‎
fifo_we_range = 0‎
wr_dqs_range = 1‎
wr_data_range = 1‎

Optimal values have been found!!‎

‎***************************************************************‎
‎ The Slave Ratio Search Program Values are... ‎
‎***************************************************************‎
PARAMETER MAX | MIN | OPTIMUM | RANGE ‎
‎***************************************************************‎
DATA_PHY_RD_DQS_SLAVE_RATIO 0x041 | 0x03f | 0x040 | 0x002‎
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x0b4 | 0x0b1 | 0x0b2 | 0x003‎
DATA_PHY_WR_DQS_SLAVE_RATIO 0x085 | 0x07f | 0x082 | 0x006‎
DATA_PHY_WR_DATA_SLAVE_RATIO 0x0f2 | 0x08a | 0x0be | 0x068‎
‎***************************************************************‎

‎===== END OF TEST =====‎

the ARM got stuck during booting after changing to the above values.

Nadav

0 JJD over 7 years ago in reply to Nadav Yafe

TI__Guru* 80310 points

After changing your GEL with the optimal values, power cycle the board, connect with JTAG, initialize the DDR, and run the tests under "AM335x DDR Tests" in the GEL scripts. Do those pass? If not, can you open up a memory window at 0x80000000 to see if the DDR memory is stable (ie, perform some peek/poke of memory). What is the behavior?

Also, what code are you booting with? Does that code perform any DDR initialization?

Regards,
James

0 Jeff Zheng over 7 years ago in reply to JJD

Prodigy 70 points

Hi James,

We have ddr iniailization code in uboot, inside MLO, it is derived from the standard ti sdk uboot, we added a new board type (copied from a ti am335x). And in our new board type, we changed the ddr iniailization code.

After change the GEL with the values generated, I tried the DDR test scripts, and it failed.

Also when using the memory browser, I can see the memory is not stable.

Each time I hit enter on the address 0x80000000, I can see somwething has changed, returning either all 0 on certain address.

I think the memry test function, write A5 to these addresses. See below, each time the result is different, it is as if the data A5A5A5A5 is in the memory, but each time the read would fail and return 0x00000000 on random addresses.

Also the 0xFFFFFFFF, I think indicate write failure during the memtest, they behave more lide the A5A5A5A5 values, more likely the memtest failed to write the A5 into those locations.

0x80000000 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x80000014 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x80000028 A5A5A5A5 A5A5A5A5 00000000 A5A5A5A5 A5A5A5A5
0x8000003C A5A5A5A5 A5A5A5A5 FFFFFFFF A5A5A5A5 A5A5A5A5
0x80000050 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x80000064 FFFFFFFF A5A5A5A5 A5A5A5A5 A5A5A5A5 00000000
0x80000078 00000000 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x8000008C A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x800000A0 A5A5A5A5 A5A5A5A5 00000000 00000000 A5A5A5A5
0x800000B4 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x800000C8 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x800000DC A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x800000F0 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x80000104 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x80000118 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5
0x8000012C A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5 A5A5A5A5

Also here is our Gel modification.

#define CMD_PHY_CTRL_SLAVE_RATIO 0x100
#define CMD_PHY_INVERT_CLKOUT 0x1

#define DATA_PHY_RD_DQS_SLAVE_RATIO 0x40
#define DATA_PHY_FIFO_WE_SLAVE_RATIO 0xB2 //RD DQS GATE
#define DATA_PHY_WR_DQS_SLAVE_RATIO 0x82
#define DATA_PHY_WR_DATA_SLAVE_RATIO 0xBE //WRITE DATA

Jeff

0 JJD over 7 years ago in reply to Jeff Zheng

TI__Guru* 80310 points

Hi Jeff, did you also use the timing spreadsheet to calculate the proper AC timing values for registers TIMING1-3? See step 1 in processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

Regards,
James

0 Nadav Yafe over 7 years ago in reply to JJD

Prodigy 130 points

Hi,

yes, we did. see attached.4571.RatioSeed_AM335x_boards.xlsx

0 JJD over 7 years ago in reply to Nadav Yafe

TI__Guru* 80310 points

Hi Nadav, there is another spreadsheet in step 1 of the wiki which calculates values for the AC timing registers in the DDR controller, which is based on the memory you are using. Please attach that along with the part number of the DDR you are using.

Regards,
James

0 Nadav Yafe over 7 years ago in reply to JJD

Prodigy 130 points

Hi,

the MPN we are using is: MT41K256M16TW-107:P (MICRON).

see attached the spreadsheet from step 1 you mentioned.

7357.AM335x_DDR_register_calc_tool.xls

0 JJD over 7 years ago in reply to Nadav Yafe

TI__Guru* 80310 points

Nadav, there are several parameters in the spreadsheet that don't look correct. For example, you have tRCD=6ns, but the memory datasheet shows 13.91ns. You also have tRAS=15, but the datasheet shows 34ns. Also, ODTLon has a value that produced an error in the spreadsheet. Please fix these and other possible issues in the spreadsheet.

Regards,
james

0 Nadav Yafe over 7 years ago in reply to JJD

Prodigy 130 points

James,

the values i used are for 400Mhz clock speed. even though the part is of higher grade we are working at 400Mhz.
which values should i use?
as for ODTLon, from the data sheet the formula is: CWL + AL - 2xCK
CWL = 5
AL = 0
This should give 3CK. is that ok?

thanks.

0 JJD over 7 years ago in reply to Nadav Yafe

TI__Guru* 80310 points

Nadav, i think you are looking at the wrong table for many of the parameters.

Since you chose tRCD-6ns, i think you are looking at the conditions used during Idd measurements (Table 9), which is incorrect. You need to look at the speed bin tables for the speed rating of your device (or the speed at which you are operating, either will work fine), and then get the rest of the parameters from the tables at the end of the datasheet (AC operating conditions)

Regards,
James

Processors

Processors forum

AM3352: DDR3 software leveling