AM3354: XIP boot fails

Lithin Karippadakan

Part Number: AM3354

Dear Sir/Madam,

In my current design, I'm using AM3354BZCZD80 in XIP mux2 boot mode. The boot mode set is SYSBOOT[4;0]=00011. Boot Sequence: UART0-SPI0-XIP-MMC0. I'm able to flash the files to FLASH through UART0 boot and if I enter the "RESET" command from there (now the system is booted on UART0 boot mode) it will reset the board and start booting from the flash. But if I powered off and on the board, it is not booting from flash at all. the board is printing "CCCCC" on the console port. Attaching the schematic portion of the same.

DDR3 is the main memory interface.

Can someone please help me to rectify the issue?

Looking forward for a positive response.

Regards,

Lithin K

Atop Technologies.SCHEMATIC1 _ 08. Local Bus & Fl.pdf

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

What software are you using? Which version?

0 Biser Gatchev-XID over 8 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Please post the processor side of the connections too.

0 Lithin Karippadakan over 8 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Dear Biser,

Following are the version of software used.

U-Boot SPL 2017.01

U-Boot 2017.01

Attaching the Schematic portion of processor also.

Regards,

Lithin K

pg5901.pdf

0 Biser Gatchev-XID over 8 years ago in reply to Lithin Karippadakan

TI__Guru**** 393215 points

What seems suspicious is the additional pulldowns on GPMC_A[23:16] through the buffer U6. I am not sure of the state of these lines at reset release time. Please check.

0 Lithin Karippadakan over 8 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Dear Biser,

Checked the states of GPMC_A[23:16], while reset release time all are in logic low level.

Regards,
Lithin K

0 Biser Gatchev-XID over 8 years ago in reply to Lithin Karippadakan

TI__Guru**** 393215 points

Another thing to check is the state of all SYSBOOT signals at reset release time. Also check that EMU0 and EMU1 are both high at that time.

0 Lithin Karippadakan over 8 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Dear Biser,

Checked the SYSBOOT pins at the reset release time. All pins behave as defined. attaching the SYSBOOT configuration details.

Checked the EMU0 and EMU1signals, both are in the high state during reset release time. Please advise how to proceed further.

Regards,

Lithin K

further.

0 Biser Gatchev-XID over 8 years ago in reply to Lithin Karippadakan

TI__Guru**** 393215 points

Another possible reason is that the NOR flash is not ready yet when the ROM code tries to access it. I see that you haven't connected the R/B signal from the NOT to GPMC_WAIT0. This could be an issue.

0 Lithin Karippadakan over 8 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Dear Biser,

Checked the pin status of Flashs RD/BY# (pin no17) while the CS0 asserts, the RD/BY# pin is in Logic high state.

Connected the RD/BY# pin of Flash to Processor GPMC_WAIT0 pin (Ball no:T17) ( a Pull-up resistor also provided), observation is same that the board is not booting on Power up.

Regards,
Lithin K

0 Marcus Cooksey over 8 years ago in reply to Biser Gatchev-XID

TI__Genius 9510 points

Lithin,

You stated that after booting from UART, flashing the image to NOR, and typing "RESET" command the system boots from FLASH successfully. Can you provide evidence (console logs) that booting is indeed from flash and not from the memory location used to setup UART boot?

Hopefully you have JTAG integrated on your board. If so, you can more accurately identify the root cause of the boot failure by dumping and analyzing ROM trace vectors as outline in the following wiki under section "Tracing vectors" :
processors.wiki.ti.com/.../AM335x_board_bringup_tips

Processors

Processors forum

AM3354: XIP boot fails