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TMS320C6748: DAC connection to C6748 via EMIF

Sung-IL
Mastermind 29770 points
Part Number: TMS320C6748
Other Parts Discussed in Thread: DAC7742, DAC902

Dear Champs,

Is it possible to connect DAC to EMIF of C6748 and transmit data to DAC continuously?

As 2ch ADC were connected to 2ch upp of C6748, I think there is only EMIF port to connect DAC and I think DAC was connected to EMIF in async mode, but I don't confident how EMIF can send waveform data to DAC continuously in async mode during a minute.

Please help to check if EMIF can work with DAC to send waveform data during some time.

Thanks and Best Regards,

SI.

  • 0
    TI__Mastermind 29560 points

    Hi SI.,

    What DAC are you hoping to use?

    I would have recommended the VPIF but its muxed with uPP, and you said you are already utilizing the uPP...

    I think it may be possible for EMIF to interface to a DAC. It probably depends on the DAC, and I would recommend proving that the signals can satisfy the DAC timing requirements first. I studied just one DAC (DAC7742). For that device, there is no clock, and very few signals. the LDAC signal can be held low for direct writes from the bus to the DAC register. Or maybe an address pin can be used or LDAC.. There might be a need to connect EMIF CS to DAC R/W and EMIF OE to DAC CS (based only on this one waveform). There is also a chance that some logic might be needed between the EMIF and the DAC.

    Back to back writes are possible from the EMIF. Probe the signals to see if the rate is fast enough and the timings are sufficiently periodic for the application.

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    TI__Mastermind 29770 points

    Hi Mark,

    Thanks for your response.

    it seemed  'Back-to-back' write can be possible with DAC7742 in EMIF, right?

    Actually, what we are considering is DAC902 and I'm afraid this is too fast and it can not be work with EMIF of C6748 in 'Back-to-back' write.

    Could you please confirm this?

    Thanks and Best Regards,

    SI.

  • 0 in reply to Sung-IL
    TI__Mastermind 29560 points
    Hi SI.

    It is not clear to me if the EMIF will operate with DAC902. I can say that the EMIF will not operate if the DAC902 runs at its maximum frequency of 165MHz.

    The theoretical maximum would be 100MHz based on the SDRAM CLK switching characteristics (min cycle = 10ns). At this clock rate, the data output delay of 7ns satisfies the DAC902 setup time of 1ns. The output hold time of 1ns is just below the DAC902 hold time requirement of 1.5ns - marginal.

    I'm unable to make any claims about the clock to data relationship in asynchronous mode. Would another signal be used to latch the data on the DAC902? Data is latched on the rising edge of its clock.

    I'm unsure if the EMIF signals will be periodic enough for the application. I suspect there will be different delays between writes - due to turn around time and internal delays. I would recommend creating a test to measure the periodicity of the output data.

    I'm also not sure what max frequency the EMIF can write to the DAC902. I suspect it will be much below the 100MHz theoretical max.

    Refer to these vaguely similar posts...

    e2e.ti.com/.../116968

    e2e.ti.com/.../117298

    Regards,
    Mark