Questions regarding the DSP p/n TMS320C6701GJCA120

Tom,

Tom Walker said:

1. Regarding the RSV signals that specify dedicated resistors, our legacy design uses 14 kilo-ohm pull up resistors for the past 8 years in production efforts. Can you please tell me if there is any impact to the DSP operation by using 14 kilo-ohm resistors instead of 20 kilo-ohm resistors?

Tom Walker said:

2. Regarding the below EMU0/EMU1 signals, our legacy design has used 3.01 kilo-ohm pull up resistors for the past 8 years in production efforts. Can you please tell me if there is any impact to the DSP operation by using 3.01 kilo-ohm resistors instead of 20 kilo-ohm resistors?

14k-ohm resistors should be sufficient. 3k-ohm resistors are a bit strong, but in most cases these should be fine. I have seen 1k-ohm resistors used in the past successfully, but considering you have had these boards in production for 8 years I do not foresee any future issues.

Tom Walker said:

3. Regarding the below PLLF/PLLG signals, our legacy design has uses R1 = 60.4 ohms, C2 = 560 pF, and C1 = 0.027 uF for the past 8 years in production efforts. Our configuration is the same as the below per DSP data sheet TMS320C6701GJCA120 except R1 and C1 are swapped. The R1 in our legacy design is common to PLLF instead of PLLG and C1 in our legacy design is common to PLLG instead of PLLF. Can you please let me know if this is a problem?

I don't see this as being an issue either but I will have to check with our product group to see if they know of a reason otherwise.

Tom Walker said:

4. Regarding decoupling capacitors DSP p/n TMS320C6701GJCA120, we have been using 4 of 0.1 uF capacitors decoupling between 1.8 Vdc core voltage and 3.3 Vdc I/O voltage in our legacy design for the past 8 years. Do you have any idea why this is necessary or what the purpose of this configuration is?

I apologize in advance if this comes off as sounding rude, but the purpose of a decoupling capacitor on the voltage pins is to help remove noise caused from other parts of the system. Are you asking about the specific value of those caps, or the number of caps used or something like that? Please clarify the question if possible.

Tom,

Here's an update on items 3 and 4.

Tom Walker said:

3. Regarding the below PLLF/PLLG signals, our legacy design has uses R1 = 60.4 ohms, C2 = 560 pF, and C1 = 0.027 uF for the past 8 years in production efforts. Our configuration is the same as the below per DSP data sheet TMS320C6701GJCA120 except R1 and C1 are swapped. The R1 in our legacy design is common to PLLF instead of PLLG and C1 in our legacy design is common to PLLG instead of PLLF. Can you please let me know if this is a problem?

From a general noise filtering/termination standpoint, I don't see any issue with reversing the PLL C1/R1 placement. 

Tom Walker said:

4. Regarding decoupling capacitors DSP p/n TMS320C6701GJCA120, we have been using 4 of 0.1 uF capacitors decoupling between 1.8 Vdc core voltage and 3.3 Vdc I/O voltage in our legacy design for the past 8 years. Do you have any idea why this is necessary or what the purpose of this configuration is?

This does sound a bit off. It seems as though this would keep the 1.8V - 3.3V supply offsets more constant relative to each other as opposed to ground, and noise from one supply plane would be injected into the other. This does not seem like the most efficient design and this is not mentioned anywhere the datasheet or any app note. It may be related to this: "systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage." I believe we usually suggest a diode in between the two rails rather than decoupling caps.

Tom Walker said:

4. Regarding decoupling capacitors DSP p/n TMS320C6701GJCA120, we have been using 4 of 0.1 uF capacitors decoupling between 1.8 Vdc core voltageand 3.3 Vdc I/O voltage in our legacy design for the past 8 years. Do you have any idea why this is necessary or what the purpose of this configuration is?

I suspect the purpose is to provide a path for return currents of lines referenced to the split power plane. 

Most of the return current travels on back to the source part on the path of lowest impedance, which is mostly on the plane right over/under the high-speed trace.  If there is a break in that plane, the return currents have to take a circuitous path, leading to EMI and possibly signal integrity issues.  Good decoupling very near to where high-speed signals cross the break provides a return path for these signals.  It allows you to route high-speed traces over the split in a split power plane.