AMIC110: Flash and DDR for AMIC110

Antonio Faggio

Part Number: AMIC110
Other Parts Discussed in Thread: TMDXICE110

Hello All,

My customer, from the HW point of view, is starting to design an Ethernet multiprotocol board based on the AMIC110 component and on the AMIC110 ICE (TMDXICE110) development board.

They noticed that the SPI W25Q64FVZPIG and the DDR provided in the development board are about to become obsolete.

In order not to include obsolete components on customer board, I want to ask if you have a list of flash and "alternative" DDRs already approved (tested) for AMIC110 to share with customer or at least any suggestions/comments on how to choose the ones that best matches with our ds specs.

Many Thanks,

Antonio

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

We don't have a list of compatible memories. It's the customer's responsibility to choose components for their design. Requirements are listed in the device datasheet/TRM.

0 Antonio Faggio over 7 years ago in reply to Biser Gatchev-XID

TI__Expert 7720 points

Hello,

Thanks for reply.
Which device datasheet specs do you refer to? This one may be: www.ti.com/.../AMIC110
Since the choice of alternative memories depend on both hw but also sw considerations customer think they should be "homologated" by TI. (he also imagines that the drivers for the management of these memories are inside the stack provided for the different protocols, or in any case on a basic part for memory management).
Anyway if there is a document that describes the specific hw and sw that must have these memories to be compatible, that would be great .
Or we do not provide none of this?
Many Thanks,

Antonio

0 Biser Gatchev-XID over 7 years ago in reply to Antonio Faggio

TI__Guru**** 393215 points

Antonio,

SPI flash memory requirements are listed in section 26.1.8.6 of the AM335x/AMIC110 Technical Reference Manual Rev. P.
DDR design guidelines are listed in section 7.7.2 of the AMIC110 Datasheet Rev. B.

0 Antonio Faggio over 7 years ago in reply to Biser Gatchev-XID

TI__Expert 7720 points

Hello,
I also add another doubt about the size of the DDR.
A 4Gb memory is put on the EVB, but is such a big memory necessary?
My customer has 1Gb DDR and he wants to use them on the multiprotocol board: what is the minimum size required for DDR?
Is there also a value (or range) for the size of the internal bank?
Memories of different sizes could in fact differ not only for number of banks but also for their size (customer does not want the DDR to be therefore incompatible with the sw written from TI).
Many Thanks,

Antonio

0 Garrett Ding over 7 years ago in reply to Antonio Faggio

TI__Mastermind 43296 points

Antonio,

1Gb DDR is sufficient for multi-protocol design. None of existing industrial protocols in PRU-ICSS sw package requires more than 3MB DDR. EtherCAT can even run with on-chip memory, i.e. without DDR on AMIC110 board. The minimum size required for DDR varies as it depends on which protocols need to be run concurrently.

There is no specific requirement for DDR internal banks for supporting multi-protocol.

Regards,
Garrett

0 Antonio Faggio over 7 years ago in reply to Garrett Ding

TI__Expert 7720 points

Hello Garrett,

Thanks for the reply.

Therefore if I understood correctly there are no problems in putting DDR of different sizes (smaller) than the one in the EVB, given that they are sized for the protocols you want to use (I also saw that for Ethercat there is no need for DDR).

The management of the different size of the blocks it seems to me to be confirmed that it is managed directly by the TI SW, so it is not a problem, correct?

QUESTION: Is there is an automatic management of the block size or should it be set in some file with the characteristics of the memory? Example: Timings, sizes...

Many Thanks,

Antonio

0 Garrett Ding over 7 years ago in reply to Antonio Faggio

TI__Mastermind 43296 points

Hi Antonio,

That's correct - there are no problems in putting DDR of different sizes (smaller) than the one in the EVB...

The DDR configuration is performed in second boot loader (SBL) from Processor SDK in the case of AMIC110 (AM3x/AM4x).Though the PRU-ICSS industrial sw doesn't have specific requirement for the DDR blocks, users do need to manage the DDR configuration (timings, sizes...) in the SBL (see packages\ti\starterware\bootloader\src\am335x\sbl_am335x_platform_ddr.c).

Regarding the an automatic management of DDR, For AM57x, we published xls based EMIF tool and documented in the application report