Linux/AM5728: PCIe driver development

biswajit panigrahi

Part Number: AM5728

Tool/software: Linux

Hi ,

we have a custom board in which FPGA is communicating over PCIe.processor will be configured as ROOT COMPLEX and FPGA will be configured as END POINT.

We need to write the driver for the same.

We are using ti-processor-sdk-linux-am57xx-evm-04.01.00.06.

Since i am new in driver development,Currently I am studying PCIe Controller chapter of TRM.

Please suggest me any sample pcie driver which i should take it as reference and also DTS modification.

Regards,

Biswajit

over 7 years ago

0 Rex Chang over 7 years ago

TI__Guru 50170 points

Hi, Biswajit,

You should be able to find these info on internet. They are not specific to TI. For TI PCIe device tree binding info, please refer to linux/Documentation/devicetree/bindings/pci/ti-pci.txt.

Rex

0 biswajit panigrahi over 7 years ago in reply to Rex Chang

Intellectual 680 points

Hi Rex,
Thanks a lot for your immediate reply.Really appreciate you.
If you can show any pcie driver from PSDK, then it will be really helpful to me.

Regards,
Biswajit

0 Rex Chang over 7 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

PCIe driver should be located in linux/drivers/pci directory. RC for AM57x devices is in dwc/pci-dra7xx.c

Rex

0 biswajit panigrahi over 7 years ago in reply to Rex Chang

Intellectual 680 points

Hi Rex,
If i understood correctly then i should take pci-dra7xx.c as reference and develop the code for FPGA communication.
Let me know if i understood in a wrong way.

One more doubt is whether i should use platform driver registration the way its used in pci-dra7xx.c or I can use pci_register_driver API ?

Regards,
Biswajit

0 Rex Chang over 7 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

I think what you want is an example of the data communication between RC and EP, not necessary of EP configuration. Please refer to drivers/misc/pci_endpoint_test.c(RC) and drivers/pci/endpoint/functions/pci-epf-test.c(EP). We connect 2 AM57x EVMs, one as RC and the other EP to run this endpoint functionality test for read, write, copy, etc. For more detail, please refer the EP User's Guide, software-dl.ti.com/.../Foundational_Components_Kernel_Drivers.html

Hope this is what info you want.
Rex

0 biswajit panigrahi over 7 years ago in reply to Rex Chang

Intellectual 680 points

Hi Rex,
Yes I want to communicate with FPGA over PCIE. In that Processor will be Root Complex and FPGA will be Endpoint.
So if i understood correctly then I need to write a misc driver as suggested example(drivers/misc/pci_endpoint_test.c) only .
Since am57xx-evm.dts(ti-processor-sdk-linux-am57xx-evm-04.01.00.06) doesn't have PCIE configuration for Root comple,If you can share the required modification in DTS file for processor as RC will be really helpful.We are using PCIE_TXP0,PCIE_TXN0,PCIE_RXP0,PCIE_RXN0.

Regards,
Biswajit

0 Rex Chang over 7 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

Does TI's DTS for RC and EP work for you?

Rex

0 biswajit panigrahi over 7 years ago in reply to Rex Chang

Intellectual 680 points

Hi Rex,
I followed the processors.wiki.ti.com/.../Linux_Core_PCIe_Driver_User's_Guide output of lspci is below.

When I executed lspci the Out put was:
# lspci
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01)

# lspci -vv

00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting

With this can I confirm that PCI with Root Complex is configured?
Else let me know how can i confirm that ?

For communicating with FPGA ,i feel i have to configure PCIE_TXP0,PCIE_TXN0,PCIE_RXP0,PCIE_RXN0 have to register the pci driver.
Please let me know with respect to DTS if any updation is required or not.

Regards,
Biswajit

0 Rex Chang over 7 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

By default, the EVM is configured as RC in the released package. In the User's Guide, there is a section about PCIe EP. Hope that info is helpful. You can also check how the EP is configured in the dts file in the release.

software-dl.ti.com/.../Foundational_Components_Kernel_Drivers.html

Rex

0 biswajit panigrahi over 7 years ago in reply to Rex Chang

Intellectual 680 points

Hi REX,
In FPGA, linux will not be running.
still do i need to configure the PCIE in EP mode ?
In the shared example,one board will be RC and other board will be EP. So on one board PCIE is configured as RC and in other board PCIE is configured as EP.
Where as in my case, i need to write RC driver which wiil do the transaction with EP(FPGA).
So please clarify that whether i need to write two driver one for RC(example:pci_endpoint_test.c(RC)) and pci-epf-test.c(EP)
OR one driver is required.

Regards,
Biswajit

0 Rex Chang over 7 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

In your case, the EVM is RC, so you don't need to configure it as EP and it can't be in both mode. In our setup, the pci_endpoint_test.c is run on RC and pci_epf_test.c on EP. I am not familiar how FPGA should work, but assume something similar to pci_endpoint_test.c on RC and pci-epf-test on FPGA.

Rex

0 biswajit panigrahi over 6 years ago in reply to Rex Chang

Intellectual 680 points

Hi Rex,
thanks a lot for your support.
Just wanted to know whether i need to do the pin configuration of PCIE_TXP0,PCIE_TXN0,PCIE_RXP0,PCIE_RXN0 in DTS file or not.
If any other configuration required with respect to DTS please let me know.

Regards,
Biswajit

0 Rex Chang over 6 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

The pin configuration depends on your FPGA. If it has dedicated pins like AM57x, then no configuration is required. Otherwise, pinctrl dts entry has to be added.

Rex

0 biswajit panigrahi over 6 years ago in reply to Rex Chang

Intellectual 680 points

HI Rex,

I have gone through the

link ,but i didn't find any PIN connectivity information between RC & EP.

I have attached our schematic of pin diagram and let me know whether i need to any pin configuration or not.

Regards,

Biswajit

0 Rex Chang over 6 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

I am not sure how I can further help you here. If you have TI related issue, please submit a new thread.

Thanks!

Rex

0 biswajit panigrahi over 6 years ago in reply to Rex Chang

Intellectual 680 points

Hi Rex,

I think i couldn't put my questions properly.

The example Link which you have shared: regarding communicating two EVM boards.

Can you please share the processor pin information which are used pci communication.

Regards,

Biswajit

0 Rex Chang over 6 years ago in reply to biswajit panigrahi

TI__Guru 50170 points

Hi, Biswajit,

The schematics can be found in www.ti.com.
AM571x IDK: www.ti.com/.../TMDXIDK5718
AM572x IDK: www.ti.com/.../TMDXIDK5728
AM5728 GP EVM: www.ti.com/.../TMDSEVM572X

Rex

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Linux/AM5728: PCIe driver development