Hi All,
Regarding the problem I reported that SYN_MODE.FLDSTAT bit toggles erractically, I asked another community member Wending Weng, and he told me that
I have never made it work in BT.656 mode, however, I managed to make it work in raw sync mode.
Please also refer to his original post.
I could not understand this. Did I missed anything in the VPFE manual or have made mistakes in my experiment? I don't believe a dedicated digital media processor cannot provide this basically required information for real-time video processing.
Whenever we receive the FF 00 00 FVH if the FVH field indicates a start of active vide we generate a active high pulse that is at the same time as the FVH data. This occurs before the polarity selection for the pulse so for 656 data you should set the HD polarity to negative. If the FVH code marks it as the start of the blanking period at the end of the frame we take the VD high and it remains high until we get the FVH code marking the first active line for the next frame. So again for this case you should set the VD polarity to negative so that the first pixel of the first line seen internally is the first active pixel
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/71024/262696.aspx
From what Mr. David Smith has described, it is clear tha VPFE make use of the FVH information embedded in the 656 stream, which can also be inferred from the fact that SDOFST can be used to configure line offset between 0 and 1 fields. Clearly VPFE extracts and uses this information, but does it provide means to get this field identification information? Or otherwise how can the programmer / ISR know which field does the VDINT0/VDINT1 is coming from? Without this how can interlacing artifacts be avoided?
I sincerely wish to get a response on this question, as well as the related primary post Several related VPFE questions.
Regards,
Zheng
