Hyperlink Specification

Hi,

you can find the Hyperlink User's Guide here:

http://focus.ti.com/lit/ug/sprugw8/sprugw8.pdf

Kind regards,

one and zero

I have looked through the Hyperlink User Guide and it does not provide all the necessary information to create a Hyperlink interface. Details such as the scrambling algorithm used, what are the idle and or sync code words. In one section it says the encoding method is like 8b9b and then later on it says it is GFP 32/33. The Hyperlink User Guide is a good overview but I think it lacks the necessary low level details. If I missed them in my reading, please point me to the relevant sections. 

Thank you Dave.

Do you know if the IP is TI's or will it be provided through a 3rd party? Also, will this be something TI will charge users a license fee or will it be free to use with TI's products?

Which FPGA companies are you working with?

Colin, Norton,

We'll include details on the FPGA families and on licensing and support options when we make a formal announcement of the IP release for FPGA. We're still working through some of the details on each.

Best regards,

Dave

Dave,

Any progress on the formal annoucement?

Rgds

Flemming

Hi Dave,

Any news?  will this be a closed standard?  Or will we be able to use it?

If the HL is closed and if TI is still working technical details, that's fine, but is there at least any news about the FPGA vendors, licensing costs (if any)?

Regards,

Robert

I assume the IP won't require a specific FPGA vendor? (Any FPGA with 12.5Gbps SerDes on market would work?)

Thanks!

Any updates on the availability of a Hyperlink to FPGA implementation?

Again, if you need help with this IP all I need is the Hyperlink specification and I can get it up and running. I'm fairly proficient at these serial communication protocols in the FPGA, having done a PCIe and SRIO from scratch.

But I understand if you want to keep all the work and hassles to yourselves! ;) 

Any updates here?

All,

The FPGA release for HyperLink is not yet available. We'll make an announcement with details on the availability and collateral as we get near to having a release. We're projecting something around the end of the year.

We do have HyperLink available on the C6678 and C6670 EVMs, and you are able to create a setup with two EVMs talking to each other over the interface (through a cable to be purchased separately) such that initial work on the DSP can begin already.

Best regards,

Dave

Dave, 

I wonder why is it so difficult to describe _NOW_ FPGA families that have trancievers compatible with Hyperlink SERDES?

You know, I have spent about 10 months trying to get similar information from TI engineers about VLYNQ implementation for FPGA. And I ended up with nothing! TI answer was something like "please, refer to FPGA vendor for VLYNQ IPs", XILINX' answer was "VLYNQ IP is obsolete", ALTERA don't have any answer about VLYNQ on the web. Note that your answer in this topic is absolutely the same as official TI's answer about VLYNQ couple of years ago. And we know results!

Looking through the Hyperlink User Guide, watching absolutely the same awkward policy of hiding any details (as it was and still is with VLYNQ), I can suppose that Hyperlink is an upgrade of VLYNQ transport layer, made by TI collaborating the same guys who did VLYNQ for C6424.

Obviously, Hyperlink is much more powerful than any other C66X DSP I/O and is main candidate for inter-precessor communication. Obviously, the case of two processors is not as interesting as N processors plus some i/o hub. So, we need FPGA on Hyperlink! I hope TI guys understand it well and would not object or prevent customers in their tries to find the most effective solution. And, I think, imposing some IP from one FPGA vendor cannot be the most effective solution for everyone.

Best regards, Vladimir

Vladimir Dashevsky said:

Dave, 

I wonder why is it so difficult to describe _NOW_ FPGA families that have trancievers compatible with Hyperlink SERDES?

You know, I have spent about 10 months trying to get similar information from TI engineers about VLYNQ implementation for FPGA. And I ended up with nothing! TI answer was something like "please, refer to FPGA vendor for VLYNQ IPs", XILINX' answer was "VLYNQ IP is obsolete", ALTERA don't have any answer about VLYNQ on the web. Note that your answer in this topic is absolutely the same as official TI's answer about VLYNQ couple of years ago. And we know results!

Looking through the Hyperlink User Guide, watching absolutely the same awkward policy of hiding any details (as it was and still is with VLYNQ), I can suppose that Hyperlink is an upgrade of VLYNQ transport layer, made by TI collaborating the same guys who did VLYNQ for C6424.

Obviously, Hyperlink is much more powerful than any other C66X DSP I/O and is main candidate for inter-precessor communication. Obviously, the case of two processors is not as interesting as N processors plus some i/o hub. So, we need FPGA on Hyperlink! I hope TI guys understand it well and would not object or prevent customers in their tries to find the most effective solution. And, I think, imposing some IP from one FPGA vendor cannot be the most effective solution for everyone.

Best regards, Vladimir

That is a disconcerting story Vladimir.

We are approaching the year mark on this issue. I could have had an interface up and running in an FPGA by this point if the Hyperlink spec had been made available so customers could use this TI product.

I agree with you, Vladimir, it really does not make any sense for TI to keep it closed. 

Colin,

I guess that situation is not so desparate as it seems. I have walked smack in a similar situation with VLYNQ on C6424. I had seen its datasheet and VLYNQ user guide and decided VLYNQ is an acceptable FPGA interface for a SoM. Troubles came soon after samples of the new board were produced. We could not get any support from TI and had no other way as to study signals on EVM. So, now I have some experience what to do. I think we could share our views of the problem. If you agree, please, write me a message to this e-mail: vladimir.dashevsky@gmail.com.

Best regards, Vladimir

Vladimir, Colin,

We are pleased with your strong interest in the HyperLink IP, and understand that you have been anxiously waiting for us to enable FPGA designs to work with our DSPs. TI will be facilitating the release on FPGAs, as indicated previously, but we are not there yet. We expect this to occur in the coming months, and will be posting information on licensing as well as collateral through the product pages. We are not supporting customers designing their own implementation on FPGA to a published standard, rather we will be releasing to specific FPGA targets. The initial FPGA part numbers are not yet announced, but this will be provided when we give a more definitive schedule.

We are not advising to design a solution until the FPGA targets, release schedule, and design collateral are made available.

Best regards,

Dave

Any updates here?

gomo said:

Any updates here?

Yes gomo. I have a project that could use a hybrid DSP and FPGA solution but the bandwidth requirements are such that the Rapid IO interface will not be sufficient to connect a C667x DSP to the FPGA. Plus, the intensive signal processing routines in the FPGA take days to par in the Xilinx software and a few hours in Altera. 

Colin,

I want to add that Hyperlink is much faster than any of existing FPGA families. The only FPGAs which can support 12.5 Gpbs per lane are the 7th generation of Xilinx, Virtex-7 or Kintex-7 or Artix-7 (at a half speed). As I know, Altera devices (e.g. Stratix-IV or -V) are either too expensive or have too slow links comparing to Hyperlink speed. And, another problem is a 8b9b encoding scheme, which is not supported by most SERDES implemented in FPGA. That is, it will take some efforts to support the link speed beyond raw SERDES, encoding and decoding stream data.

Best regards, Vladimir

Earlier you announced support for hyperlink to certain FPGAs.  Which ones?  I have a requirement for 2.4GSPS or 28.8 gbps.  Is this possible with the hyperlink IP that you mentioned previously.  If not, what is the best way forward?  Can I map the fpga onto the DDR3 bus maybe?

thank you,

Dan

Umm,

just found the answer to my question:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/133393.aspx

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/b/announcements/archive/2012/07/19/integre-technologies-announces-hyperlink-dsp-interface-fpga-core.aspx

Dan