TDA2PXEVM: PHY_ALIVE signal with a switch between PHY and TDA2px

tejeswini jayaram

Part Number: TDA2PXEVM

Hello,

I am working with an ECU where PHY is connected using ENET 5 PORT SWITCH to TDA2px. In the design MDC and MDIO are not used. But, Port switch is clocked with 25MHz OSC. Can the PHY be working without MDC and MDIO in this scenario?

Regards,

Tejeswini

over 6 years ago

0 Prasad Jondhale over 6 years ago

TI__Mastermind 27743 points

Hello Tajeswini,

Not sure I understand the how TDA is connected. Is TDA connected to switch via PHY?
Can you please share block diagram of connections? If it is confidential to be shared on public e2e, you can send it via mail [a0132233@ti.com]

0 Prasad Jondhale over 6 years ago in reply to Prasad Jondhale

TI__Mastermind 27743 points

Hello Tajeswini,

You need to disable MDIO as there is no phy in the system. Please configure nsp like below in function GMACSW_getConfig.

pGMACSWConfig->macInitCfg[1].mdioModeFlags = MDIO_MODEFLG_NOPHY;
pGMACSWConfig->macInitCfg[i].macConnectionType = MAC_CONNECTION_TYPE_RGMII_FORCE_1000_FULL;

0 tejeswini jayaram over 6 years ago in reply to Prasad Jondhale

Prodigy 200 points

Hello Prasad,

I see fd error 64 (HOSTDOWN). Firewall in the pc i am connecting to ECU is enabled. Could that cause this error or could it be another issue? Do you have suggestions for debug? PHY_ALIVE register is 0 (Since there is no link, this is expected, rite?)

Thanks.

Regards,

Tejeswini

0 Prasad Jondhale over 6 years ago in reply to tejeswini jayaram

TI__Mastermind 27743 points

Hello Tejeswini,

Before that are you able to get an IP via DHCP?
Also can I recommend to use Ubuntu machine for testing so you wont face firewall issues?

0 tejeswini jayaram over 6 years ago in reply to Prasad Jondhale

Prodigy 200 points

Hi Prasad,

How can i check getting IP via DHCP is successful? I cannot ping with the config IP. Lost packets.

Regards,

Tejeswini

0 tejeswini jayaram over 6 years ago in reply to tejeswini jayaram

Prodigy 200 points

Hello Prasad,

I am configuring for static IP address from NDK Config file. I see the source ip address and destination ip address extract from IP header in NSP. Is there a better way to see if assigning IP address is good?

Stepping into code shows that IPTX_ERROR_HOSTDOWN is returned from below condition.

/* If the route is down, we're still unreachable */

if( !(w & FLG_RTE_UP) )
{
if( !(Flags & FLG_IPTX_FORWARDING) )
ips.Localnoroute++;
else
{
ips.Cantforward++;
ICMPGenPacket(pIpHdr,hIFRx,ICMP_UNREACH,ICMP_UNREACH_HOST,0);
}
PBM_free( pPkt );
return( IPTX_ERROR_HOSTDOWN );
}

Regards,
Tejeswini

0 Prasad Jondhale over 6 years ago in reply to tejeswini jayaram

TI__Mastermind 27743 points

Hello Tejeswini,

I assume you are using TDA in gigabit mode. Have you configured RGMII internal delays?

Below i am copying delay config function from ndk_nsp_hooks.c. Make sure this matches with your switch delay configuration. For more details consult your switch vendor.

/* Disable RGMII Internal delays (RGMIIID). By default it is enabled */
void LOCAL_disableRGMIIInternalDelays(void)
{
uint32_t regValue;
/* Disable RGMII half cycle delay for ES2.0 silicon */
regValue = CTRL_MODULE_CTRL_CORE_SMA_SW_1;
/* Disable half cycle delay for RGMII0 */
regValue |= ((UInt32)0x1U << 25U);
/* Disable half cycle delay for RGMII1 */
regValue |= ((UInt32)0x1U << 26U);
CTRL_MODULE_CTRL_CORE_SMA_SW_1 = regValue;
}

Also once this is done, please share values of full GMAC register dump?

0 tejeswini jayaram over 6 years ago in reply to Prasad Jondhale

Prodigy 200 points

Hello Prasad,

Yes. I am operating TDA in gigabit mode. I found delay requirement from ENET port switch datasheet as "RGMII requires and external delay of between 1.5 ns and 2 ns on TXC and RXC" and configured delay for TXC ad RXC as in attachment delay_config.txt.

Other config for RGMII mode found in switch datasheet is in the image below.

Attached Full GMAC register dump in GMAC_registers.dat (with internal delay disable).

Regards,

Tejeswini

Fullscreen delay_config.txt Download

#define CTRL_MODULE_CTRL_WKUP_ID_CODE  (*(volatile uint32_t*)(0x4AE0C204))
#define CTRL_MODULE_CTRL_CORE_SMA_SW_1 (*(volatile uint32_t*) (0x4A002534))

#define CFG_IO_DELAY_BASE           (0x4844A000)
#define CFG_IO_DELAY_LOCK           (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x02C))

#define CFG_IO_DELAY_UNLOCK_KEY     (0x0000AAAA)
#define CFG_IO_DELAY_LOCK_KEY       (0x0000AAAB)

#define CFG_IO_DELAY_ACCESS_PATTERN (0x00029000)
#define CFG_IO_DELAY_LOCK_MASK      (0x400)

uint32_t PlatformGetSiliconRev(void)
{

uint32_t siliconRev;

siliconRev = CTRL_MODULE_CTRL_WKUP_ID_CODE;

siliconRev = (siliconRev & 0xF0000000U) >> 28U;

return (siliconRev);

}

if (2U != PlatformGetSiliconRev())
{
 /* Global unlock for I/O Delay registers */
 CFG_IO_DELAY_LOCK = CFG_IO_DELAY_UNLOCK_KEY;

 (*(volatile uint32_t*) 0x4844A740) = (CFG_IO_DELAY_ACCESS_PATTERN
 & ~CFG_IO_DELAY_LOCK_MASK);
 delta = 0x2; /* Delay value to add to calibrated value */
 regValue = (*(volatile uint32_t*) 0x4844A740) & ~0xFFFFFC00;
 coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
 fine = (regValue & 0x1F) + (delta & 0x1F);
 fine = (fine > 0x1F) ? (0x1F) : (fine);
 regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK
 | ((coarse << 5) | (fine));
 (*(volatile uint32_t*) 0x4844A740) = regValue;


 (*(volatile uint32_t*) 0x4844A6F0) = (CFG_IO_DELAY_ACCESS_PATTERN
 & ~CFG_IO_DELAY_LOCK_MASK);
 delta = 0x2; /* Delay value to add to calibrated value */
 regValue = (*(volatile uint32_t*) 0x4844A6F0) & ~0xFFFFFC00;
 coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
 fine = (regValue & 0x1F) + (delta & 0x1F);
 fine = (fine > 0x1F) ? (0x1F) : (fine);
 regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK
 | ((coarse << 5) | (fine));
 (*(volatile uint32_t*) 0x4844A6F0) = regValue;

}
else
{
/* Disable RGMII half cycle delay for ES2.0 silicon */
regValue = CTRL_MODULE_CTRL_CORE_SMA_SW_1;
/* Disable half cycle delay for RGMII0 */
regValue |= (0x1 << 25U);
/* Disable half cycle delay for RGMII1 */
regValue |= (0x1 << 26U);
CTRL_MODULE_CTRL_CORE_SMA_SW_1 = regValue;
}

. GMAC_registers.dat

Regards,

Tejeswini

0 Prasad Jondhale over 6 years ago in reply to tejeswini jayaram

TI__Mastermind 27743 points

Tejeswini,

Can't figure out anything from delay_config.txt. Which part of "if" loop is getting executed?

Have you configured any delays in Switch? If not, enable delays in TDA using earlier shared function.

Please dump register data uisng registers window in CCS so it would have registers addresses with value. Right click and export there.
I can't figure out anything from what you have shared.

0 tejeswini jayaram over 6 years ago in reply to Prasad Jondhale

Prodigy 200 points

Hi Prasad,

If condition for adding delay is being executed. And, i am not sure if the switch is configured for the delay. I will update when i have an answer for that. Please find the attached registers dump in txt format. GOOD TX frames are actually incremented in STAT register.

Regards,

Tejeswini

Fullscreen gmacsw_regs.txt Download

521177 21
R SPF1_SPF_IDVER 0x0000000B 0x00280100
R SPF1_SPF_STATUS 0x0000000B 0x00000000
R SPF1_SPF_CONTROL 0x0000000B 0x00000000
R SPF1_SPF_DROPCOUNT 0x0000000B 0x00000000
R SPF1_SPF_SWRESET 0x0000000B 0x00000000
R SPF1_SPF_PRESCALE 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_0 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_1 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_2 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_3 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_0 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_1 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_2 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_3 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_4 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_5 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_6 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_7 0x0000000B 0x00000000
R SPF1_SPF_INSTRW2 0x0000000B 0x00000000
R SPF1_SPF_INSTRW1 0x0000000B 0x00000000
R SPF1_SPF_INSTRW0 0x0000000B 0x00000000
R SPF1_SPF_INSTR_CTL 0x0000000B 0x00000000
R SPF1_SPF_LOG_BEGIN 0x0000000B 0x00000000
R SPF1_SPF_LOG_END 0x0000000B 0x00001000
R SPF1_SPF_LOG_HWPTR 0x0000000B 0x00000000
R SPF1_SPF_LOG_SWPTR 0x0000000B 0x00000000
R SPF1_SPF_LOG_MAP0 0x0000000B 0x00000000
R SPF1_SPF_LOG_MAP1 0x0000000B 0x00000000
R SPF1_SPF_LOG_THRESHk_0 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_1 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_2 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_3 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_4 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_5 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_6 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_7 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_8 0x0000000B 0x0000000A
R SPF1_SPF_INTCNT 0x0000000B 0x00000001
R SPF1_SPF_INT_RAW 0x0000000B 0x00000000
R SPF1_SPF_INT_MASKED 0x0000000B 0x00000000
R SPF1_SPF_MASK_SET 0x0000000B 0x00000000
R SPF1_SPF_MASK_CLR 0x0000000B 0x00000000
R SPF2_SPF_IDVER 0x0000000B 0x00280100
R SPF2_SPF_STATUS 0x0000000B 0x00000000
R SPF2_SPF_CONTROL 0x0000000B 0x00000000
R SPF2_SPF_DROPCOUNT 0x0000000B 0x00000000
R SPF2_SPF_SWRESET 0x0000000B 0x00000000
R SPF2_SPF_PRESCALE 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_0 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_1 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_2 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_3 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_0 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_1 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_2 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_3 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_4 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_5 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_6 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_7 0x0000000B 0x00000000
R SPF2_SPF_INSTRW2 0x0000000B 0x00000000
R SPF2_SPF_INSTRW1 0x0000000B 0x00000000
R SPF2_SPF_INSTRW0 0x0000000B 0x00000000
R SPF2_SPF_INSTR_CTL 0x0000000B 0x00000000
R SPF2_SPF_LOG_BEGIN 0x0000000B 0x00000000
R SPF2_SPF_LOG_END 0x0000000B 0x00001000
R SPF2_SPF_LOG_HWPTR 0x0000000B 0x00000000
R SPF2_SPF_LOG_SWPTR 0x0000000B 0x00000000
R SPF2_SPF_LOG_MAP0 0x0000000B 0x00000000
R SPF2_SPF_LOG_MAP1 0x0000000B 0x00000000
R SPF2_SPF_LOG_THRESHk_0 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_1 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_2 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_3 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_4 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_5 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_6 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_7 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_8 0x0000000B 0x0000000A
R SPF2_SPF_INTCNT 0x0000000B 0x00000001
R SPF2_SPF_INT_RAW 0x0000000B 0x00000000
R SPF2_SPF_INT_MASKED 0x0000000B 0x00000000
R SPF2_SPF_MASK_SET 0x0000000B 0x00000000
R SPF2_SPF_MASK_CLR 0x0000000B 0x00000000
R MDIO_MDIO_VER 0x0000000B 0x40070106
R MDIO_MDIO_CONTROL 0x0000000B 0x41000059
R MDIO_MDIO_ALIVE 0x0000000B 0x00000000
R MDIO_MDIO_LINK 0x0000000B 0x00000000
R MDIO_MDIO_LINKINTRAW 0x0000000B 0x00000000
R MDIO_MDIO_LINKINTMASKED 0x0000000B 0x00000000
R MDIO_MDIO_USERINTRAW 0x0000000B 0x00000000
R MDIO_MDIO_USERINTMASKED 0x0000000B 0x00000000
R MDIO_MDIO_USERINTMASKSET 0x0000000B 0x00000000
R MDIO_MDIO_USERINTMASKCLR 0x0000000B 0x00000000
R MDIO_MDIO_USERACCESS0 0x0000000B 0x00000000
R MDIO_MDIO_USERPHYSEL0 0x0000000B 0x00000000
R MDIO_MDIO_USERACCESS1 0x0000000B 0x00000000
R MDIO_MDIO_USERPHYSEL1 0x0000000B 0x00000000
R STATS_GOOD_RX_FRAMES 0x0000000B 0x00000000
R STATS_BROADCAST_RX_FRAMES 0x0000000B 0x00000000
R STATS_MULTICAST_RX_FRAMES 0x0000000B 0x00000000
R STATS_PAUSE_RX_FRAMES 0x0000000B 0x00000000
R STATS_RX_CRC_ERRORS 0x0000000B 0x00000000
R STATS_RX_ALIGN_CODE_ERRORS 0x0000000B 0x00000000
R STATS_OVERSIZE_RX_FRAMES 0x0000000B 0x00000000
R STATS_RX_JABBERS 0x0000000B 0x00000000
R STATS_UNDERSIZE_RX_FRAMES 0x0000000B 0x00000000
R STATS_RX_FRAGMENTS 0x0000000B 0x00000000
R STATS_RX_OCTETS 0x0000000B 0x00000000
R STATS_GOOD_TX_FRAMES 0x0000000B 0x00000002
R STATS_BROADCAST_TX_FRAMES 0x0000000B 0x00000002
R STATS_MULTICAST_TX_FRAMES 0x0000000B 0x00000000
R STATS_PAUSE_TX_FRAMES 0x0000000B 0x00000000
R STATS_DEFERRED_TX_FRAMES 0x0000000B 0x00000000
R STATS_COLLISIONS 0x0000000B 0x00000000
R STATS_SINGLE_COLLISION_TX_FRAMES 0x0000000B 0x00000000
R STATS_MULTIPLE_COLLISION_TX_FRAMES 0x0000000B 0x00000000
R STATS_EXCESSIVE_COLLISIONS 0x0000000B 0x00000000
R STATS_LATE_COLLISIONS 0x0000000B 0x00000000
R STATS_TX_UNDERRUN 0x0000000B 0x00000000
R STATS_CARRIER_SENSE_ERRORS 0x0000000B 0x00000000
R STATS_TX_OCTETS 0x0000000B 0x00000080
R STATS_RX_TX_64_OCTET_FRAMES 0x0000000B 0x00000002
R STATS_RX_TX_65_127_OCTET_FRAMES 0x0000000B 0x00000000
R STATS_RX_TX_128_255_OCTET_FRAMES 0x0000000B 0x00000000
R STATS_RX_TX_256_511_OCTET_FRAMES 0x0000000B 0x00000000
R STATS_RX_TX_512_1023_OCTET_FRAMES 0x0000000B 0x00000000
R STATS_RX_TX_1024_UP_OCTET_FRAMES 0x0000000B 0x00000000
R STATS_NET_OCTETS 0x0000000B 0x00000080
R STATS_RX_START_OF_FRAME_OVERRUNS 0x0000000B 0x00000000
R STATS_RX_MIDDLE_OF_FRAME_OVERRUNS 0x0000000B 0x00000000
R STATS_RX_DMA_OVERRUNS 0x0000000B 0x00000000
R SS_CPSW_ID_VER 0x0000000B 0x0019010F
R SS_CPSW_CONTROL 0x0000000B 0x00000000
R SS_CPSW_SOFT_RESET 0x0000000B 0x00000000
R SS_CPSW_STAT_PORT_EN 0x0000000B 0x00000007
R SS_CPSW_PTYPE 0x0000000B 0x00000000
R SS_CPSW_SOFT_IDLE 0x0000000B 0x00000000
R SS_CPSW_THRU_RATE 0x0000000B 0x00003003
R SS_CPSW_GAP_THRESH 0x0000000B 0x0000000B
R SS_CPSW_TX_START_WDS 0x0000000B 0x00000020
R SS_CPSW_FLOW_CONTROL 0x0000000B 0x00000001
R SS_CPSW_VLAN_LTYPE 0x0000000B 0x81008100
R SS_CPSW_TS_LTYPE 0x0000000B 0x00000000
R SS_CPSW_DLR_LTYPE 0x0000000B 0x000080E1
R SS_CPSW_EEE_PRESCALE 0x0000000B 0x00000000
R STATERAM_TX0_HDP 0x0000000B 0x00000000
R STATERAM_TX1_HDP 0x0000000B 0x00000000
R STATERAM_TX2_HDP 0x0000000B 0x00000000
R STATERAM_TX3_HDP 0x0000000B 0x00000000
R STATERAM_TX4_HDP 0x0000000B 0x00000000
R STATERAM_TX5_HDP 0x0000000B 0x00000000
R STATERAM_TX6_HDP 0x0000000B 0x00000000
R STATERAM_TX7_HDP 0x0000000B 0x00000000
R STATERAM_RX0_HDP 0x0000000B 0x48486000
R STATERAM_RX1_HDP 0x0000000B 0x00000000
R STATERAM_RX2_HDP 0x0000000B 0x00000000
R STATERAM_RX3_HDP 0x0000000B 0x00000000
R STATERAM_RX4_HDP 0x0000000B 0x00000000
R STATERAM_RX5_HDP 0x0000000B 0x00000000
R STATERAM_RX6_HDP 0x0000000B 0x00000000
R STATERAM_RX7_HDP 0x0000000B 0x00000000
R STATERAM_TX0_CP 0x0000000B 0x48486400
R STATERAM_TX1_CP 0x0000000B 0x00000000
R STATERAM_TX2_CP 0x0000000B 0x00000000
R STATERAM_TX3_CP 0x0000000B 0x00000000
R STATERAM_TX4_CP 0x0000000B 0x00000000
R STATERAM_TX5_CP 0x0000000B 0x00000000
R STATERAM_TX6_CP 0x0000000B 0x00000000
R STATERAM_TX7_CP 0x0000000B 0x00000000
R STATERAM_RX0_CP 0x0000000B 0x00000000
R STATERAM_RX1_CP 0x0000000B 0x00000000
R STATERAM_RX2_CP 0x0000000B 0x00000000
R STATERAM_RX3_CP 0x0000000B 0x00000000
R STATERAM_RX4_CP 0x0000000B 0x00000000
R STATERAM_RX5_CP 0x0000000B 0x00000000
R STATERAM_RX6_CP 0x0000000B 0x00000000
R STATERAM_RX7_CP 0x0000000B 0x00000000
R CPTS_CPTS_IDVER 0x0000000B 0x4E8A0105
R CPTS_CPTS_CONTROL 0x0000000B 0x00000005
R CPTS_CPTS_TS_PUSH 0x0000000B 0x00000000
R CPTS_CPTS_TS_LOAD_VAL 0x0000000B 0x00000000
R CPTS_CPTS_TS_LOAD_EN 0x0000000B 0x00000000
R CPTS_CPTS_INTSTAT_RAW 0x0000000B 0x00000001
R CPTS_CPTS_INTSTAT_MASKED 0x0000000B 0x00000001
R CPTS_CPTS_INT_ENABLE 0x0000000B 0x00000001
R CPTS_CPTS_EVENT_POP 0x0000000B 0x00000000
R CPTS_CPTS_EVENT_LOW 0x0000000B 0x00000000
R CPTS_CPTS_EVENT_HIGH 0x0000000B 0x00100000
R ALE_ALE_IDVER 0x0000000B 0x00290104
R ALE_ALE_CONTROL 0x0000000B 0x80000010
R ALE_ALE_PRESCALE 0x0000000B 0x0001E848
R ALE_ALE_UNKNOWN_VLAN 0x0000000B 0x3F06061F
R ALE_ALE_TBLCTL 0x0000000B 0x00000000
R ALE_ALE_TBLW2 0x0000000B 0x00000000
R ALE_ALE_TBLW1 0x0000000B 0x500040BD
R ALE_ALE_TBLW0 0x0000000B 0x32DA158A
R ALE_ALE_PORTCTL0 0x0000000B 0x00000003
R ALE_ALE_PORTCTL1 0x0000000B 0x00000003
R ALE_ALE_PORTCTL2 0x0000000B 0x00000003
R ALE_ALE_PORTCTL3 0x0000000B 0x00000000
R ALE_ALE_PORTCTL4 0x0000000B 0x00000000
R ALE_ALE_PORTCTL5 0x0000000B 0x00000000
R SL1_SL_IDVER 0x0000000B 0x00170113
R SL1_SL_MACCONTROL 0x0000000B 0x000200B9
R SL1_SL_MACSTATUS 0x0000000B 0x80000018
R SL1_SL_SOFT_RESET 0x0000000B 0x00000000
R SL1_SL_RX_MAXLEN 0x0000000B 0x000005F2
R SL1_SL_BOFFTEST 0x0000000B 0x03670000
R SL1_SL_RX_PAUSE 0x0000000B 0x00000000
R SL1_SL_TX_PAUSE 0x0000000B 0x00000000
R SL1_SL_EMCONTROL 0x0000000B 0x00000000
R SL1_SL_RX_PRI_MAP 0x0000000B 0x00000000
R SL1_SL_TX_GAP 0x0000000B 0x0000000C
R SL2_SL_IDVER 0x0000000B 0x00170113
R SL2_SL_MACCONTROL 0x0000000B 0x000200B9
R SL2_SL_MACSTATUS 0x0000000B 0x80000000
R SL2_SL_SOFT_RESET 0x0000000B 0x00000000
R SL2_SL_RX_MAXLEN 0x0000000B 0x000005F2
R SL2_SL_BOFFTEST 0x0000000B 0x02530000
R SL2_SL_RX_PAUSE 0x0000000B 0x00000000
R SL2_SL_TX_PAUSE 0x0000000B 0x00000000
R SL2_SL_EMCONTROL 0x0000000B 0x00000000
R SL2_SL_RX_PRI_MAP 0x0000000B 0x44444444
R SL2_SL_TX_GAP 0x0000000B 0x0000000C
R WR_WR_IDVER 0x0000000B 0x4EDB1902
R WR_WR_SOFT_RESET 0x0000000B 0x00000000
R WR_WR_CONTROL 0x0000000B 0x0000000A
R WR_WR_INT_CONTROL 0x0000000B 0x00030271
R WR_WR_C0_RX_THRESH_EN 0x0000000B 0x00000001
R WR_WR_C0_RX_EN 0x0000000B 0x00000001
R WR_WR_C0_TX_EN 0x0000000B 0x00000001
R WR_WR_C0_MISC_EN 0x0000000B 0x0000001C
R WR_WR_C0_RX_THRESH_STAT 0x0000000B 0x00000000
R WR_WR_C0_RX_STAT 0x0000000B 0x00000000
R WR_WR_C0_TX_STAT 0x0000000B 0x00000000
R WR_WR_C0_MISC_STAT 0x0000000B 0x00000010
R WR_WR_C0_RX_IMAX 0x0000000B 0x00000002
R WR_WR_C0_TX_IMAX 0x0000000B 0x00000002
R WR_WR_RGMII_CTL 0x0000000B 0x0000000D
R WR_WR_STATUS 0x0000000B 0x00000006
R CPDMA_CPDMA_TX_IDVER 0x0000000B 0x00180109
R CPDMA_CPDMA_TX_CONTROL 0x0000000B 0x00000001
R CPDMA_CPDMA_TX_TEARDOWN 0x0000000B 0x00000000
R CPDMA_CPDMA_RX_IDVER 0x0000000B 0x00180109
R CPDMA_CPDMA_RX_CONTROL 0x0000000B 0x00000001
R CPDMA_CPDMA_RX_TEARDOWN 0x0000000B 0x00000000
R CPDMA_CPDMA_SOFT_RESET 0x0000000B 0x00000000
R CPDMA_CPDMA_DMACONTROL 0x0000000B 0x00000000
R CPDMA_CPDMA_DMASTATUS 0x0000000B 0x80000000
R CPDMA_CPDMA_RX_BUFFER_OFFSET 0x0000000B 0x00000000
R CPDMA_CPDMA_EMCONTROL 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI0_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI1_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI2_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI3_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI4_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI5_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI6_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI7_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_INTSTAT_RAW 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_INTSTAT_MASKED 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_INTMASK_SET 0x0000000B 0x00000001
R CPDMA_CPDMA_TX_INTMASK_CLEAR 0x0000000B 0x00000001
R CPDMA_CPDMA_IN_VECTOR 0x0000000B 0x10000000
R CPDMA_CPDMA_EOI_VECTOR 0x0000000B 0x00000003
R CPDMA_CPDMA_RX_INTSTAT_RAW 0x0000000B 0x00000000
R CPDMA_CPDMA_RX_INTSTAT_MASKED 0x0000000B 0x00000000
R CPDMA_CPDMA_RX_INTMASK_SET 0x0000000B 0x00000101
R CPDMA_CPDMA_RX_INTMASK_CLEAR 0x0000000B 0x00000101
R CPDMA_CPDMA_DMA_INTSTAT_RAW 0x0000000B 0x00000000
R CPDMA_CPDMA_DMA_INTSTAT_MASKED 0x0000000B 0x00000000
R CPDMA_CPDMA_DMA_INTMASK_SET 0x0000000B 0x00000003
R CPDMA_CPDMA_DMA_INTMASK_CLEAR 0x0000000B 0x00000003
R CPDMA_CPDMA_RX0_PENDTHRESH 0x0000000B 0x00000010
R CPDMA_CPDMA_RX1_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX2_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX3_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX4_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX5_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX6_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX7_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX0_FREEBUFFER 0x0000000B 0x00000040
R CPDMA_CPDMA_RX1_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX2_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX3_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX4_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX5_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX6_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX7_FREEBUFFER 0x0000000B 0x00000000
R PORT_P0_CONTROL 0x0000000B 0x00000000
R PORT_P0_MAX_BLKS 0x0000000B 0x00000104
R PORT_P0_BLK_CNT 0x0000000B 0x00000042
R PORT_P0_TX_IN_CTL 0x0000000B 0x000040C0
R PORT_P0_PORT_VLAN 0x0000000B 0x00000000
R PORT_P0_TX_PRI_MAP 0x0000000B 0x00030003
R PORT_P0_CPDMA_TX_PRI_MAP 0x0000000B 0x76543210
R PORT_P0_CPDMA_RX_CH_MAP 0x0000000B 0x07770777
R PORT_P0_RX_DSCP_PRI_MAP0 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP1 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP2 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP3 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP4 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP5 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP6 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP7 0x0000000B 0x00000000
R PORT_P0_IDLE2LPI 0x0000000B 0x00000000
R PORT_P0_LPI2WAKE 0x0000000B 0x00000000
R PORT_P1_CONTROL 0x0000000B 0x00000000
R PORT_P1_MAX_BLKS 0x0000000B 0x00000113
R PORT_P1_BLK_CNT 0x0000000B 0x00000041
R PORT_P1_TX_IN_CTL 0x0000000B 0x080040C0
R PORT_P1_PORT_VLAN 0x0000000B 0x00000001
R PORT_P1_TX_PRI_MAP 0x0000000B 0x33221001
R PORT_P1_TS_SEQ_MTYPE 0x0000000B 0x001E0000
R PORT_P1_SA_LO 0x0000000B 0x00008A15
R PORT_P1_SA_HI 0x0000000B 0xDA32BD40
R PORT_P1_SEND_PERCENT 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP0 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP1 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP2 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP3 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP4 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP5 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP6 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP7 0x0000000B 0x00000000
R PORT_P1_IDLE2LPI 0x0000000B 0x00000000
R PORT_P1_LPI2WAKE 0x0000000B 0x00000000
R PORT_P2_CONTROL 0x0000000B 0x00000000
R PORT_P2_MAX_BLKS 0x0000000B 0x00000113
R PORT_P2_BLK_CNT 0x0000000B 0x00000041
R PORT_P2_TX_IN_CTL 0x0000000B 0x080040C0
R PORT_P2_PORT_VLAN 0x0000000B 0x00000001
R PORT_P2_TX_PRI_MAP 0x0000000B 0x33221001
R PORT_P2_TS_SEQ_MTYPE 0x0000000B 0x001E0000
R PORT_P2_SA_LO 0x0000000B 0x00008B15
R PORT_P2_SA_HI 0x0000000B 0xDA32BD40
R PORT_P2_SEND_PERCENT 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP0 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP1 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP2 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP3 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP4 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP5 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP6 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP7 0x0000000B 0x00000000
R PORT_P2_IDLE2LPI 0x0000000B 0x00000000
R PORT_P2_LPI2WAKE 0x0000000B 0x00000000

0 Prasad Jondhale over 6 years ago in reply to tejeswini jayaram

TI__Mastermind 27743 points

From register dump, the TDA is configured correctly and able to set itself for requested speed and duplex mode. Also 2 TX packets were sent out but no packets received from switch.
This can be mostly due to switch configuration, packet might be getting lost in switch. Please confirm that.

0 tejeswini jayaram over 6 years ago in reply to Prasad Jondhale

Prodigy 200 points

Hello Prasad,

Thanks. we are checking with the other team on switch configuration. Meanwhile, i have a question. I see GOOD_TX_FRAMES and BROADCAST_TX_FRAMES both are same value and i see them both incremented when i send Unicast packet not Broadcast.

Below is how i set Socket option:

setsockopt(m_txMessageInfo[msg_Id].connectionSocket, /* connectionSockt is 0.*/
SOL_SOCKET,
SO_SNDBUF,
&m_txMessageInfo[msg_Id].size,
sizeof(uint32_t));

And, not every attempt of sending packets is successful. Some return dfd error 64 that is HOST DOWN while other attempts are successful.

Is it normal?

Regards,
Tejeswini

0 Prasad Jondhale over 6 years ago in reply to tejeswini jayaram

TI__Mastermind 27743 points

Hello Tejeswini,

Yes, this is normal due to ARP all initial packets would be broadcast. Hence both good and broadcast count is getting set.

0 Prasad Jondhale over 6 years ago in reply to Prasad Jondhale

TI__Mastermind 27743 points

closing this thread due to inactivity. If any follow up question, start new or reply here.

0 tejeswini jayaram over 6 years ago in reply to Prasad Jondhale

Prodigy 200 points

Hello,

Trying to summarize the issue and current status:

1) Noticed GOOD_TX_FRAMES increments on sending frames but no frames received on Wireshark.

GOOD_RX_FRAMES increments (on trying to ping). But no response seen on PC.

2) Attached is the NDK configuration.

3) GMACSW config added as below:

pGMACSWConfig->cptsCfg.enableCPTSEvents = 1;
pGMACSWConfig->cptsCfg.cptsInputFrequency = 266000000;

pGMACSWConfig->macInitCfg[i].macConnectionType = MAC_CONNECTION_TYPE_RGMII_FORCE_1000_FULL;
pGMACSWConfig->macInitCfg[i].mdioModeFlags = MDIO_MODEFLG_NOPHY;

And, attached GMACSW registers (reg_dump). (Expected TXC and RXC at 125 MHz)

4) Pin Muxing for RGMII as below:

WR_MEM_32(0x4A003650, 0x00010000);
WR_MEM_32(0x4A003654, 0x00010000);
WR_MEM_32(0x4A003658, 0x00010000);
WR_MEM_32(0x4A00365C, 0x00010000);
WR_MEM_32(0x4A003660, 0x00010000);
WR_MEM_32(0x4A003664, 0x00010000);
WR_MEM_32(0x4A003668, 0x00050000);
WR_MEM_32(0x4A00366C, 0x00050000);
WR_MEM_32(0x4A003670, 0x00050000);
WR_MEM_32(0x4A003674, 0x00050000);
WR_MEM_32(0x4A003678, 0x00050000);
WR_MEM_32(0x4A00367C, 0x00050000);

5) Dumped switch registers while trying to ping TDA. Registers show

number of frames transmitted to the respective port since power-on or reset : Incrementing

Number of MAC-level correct frames received on the respective port since power-on or reset : Zero

Number of frames dropped for various reasons since the power-on reset : Zero

6) Disabled delay on TDA using below code (reason, delay is added on Switch side):

regValue = CTRL_MODULE_CTRL_CORE_SMA_SW_1;
/* Disable half cycle delay for RGMII0 */
regValue |= (0x1 << 25U);
/* Disable half cycle delay for RGMII1 */
regValue |= (0x1 << 26U);
CTRL_MODULE_CTRL_CORE_SMA_SW_1 = regValue;

Thanks.

Regards,

Tejeswini

Fullscreen reg_dump.txt Download

521177 21
R SPF1_SPF_IDVER 0x0000000B 0x00280100
R SPF1_SPF_STATUS 0x0000000B 0x00000000
R SPF1_SPF_CONTROL 0x0000000B 0x00000000
R SPF1_SPF_DROPCOUNT 0x0000000B 0x00000000
R SPF1_SPF_SWRESET 0x0000000B 0x00000000
R SPF1_SPF_PRESCALE 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_0 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_1 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_2 0x0000000B 0x00000000
R SPF1_SPF_RATELIMi_3 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_0 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_1 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_2 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_3 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_4 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_5 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_6 0x0000000B 0x00000000
R SPF1_SPF_CONSTj_7 0x0000000B 0x00000000
R SPF1_SPF_INSTRW2 0x0000000B 0x00000000
R SPF1_SPF_INSTRW1 0x0000000B 0x00000000
R SPF1_SPF_INSTRW0 0x0000000B 0x00000000
R SPF1_SPF_INSTR_CTL 0x0000000B 0x00000000
R SPF1_SPF_LOG_BEGIN 0x0000000B 0x00000000
R SPF1_SPF_LOG_END 0x0000000B 0x00001000
R SPF1_SPF_LOG_HWPTR 0x0000000B 0x00000000
R SPF1_SPF_LOG_SWPTR 0x0000000B 0x00000000
R SPF1_SPF_LOG_MAP0 0x0000000B 0x00000000
R SPF1_SPF_LOG_MAP1 0x0000000B 0x00000000
R SPF1_SPF_LOG_THRESHk_0 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_1 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_2 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_3 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_4 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_5 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_6 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_7 0x0000000B 0x0000000A
R SPF1_SPF_LOG_THRESHk_8 0x0000000B 0x0000000A
R SPF1_SPF_INTCNT 0x0000000B 0x00000001
R SPF1_SPF_INT_RAW 0x0000000B 0x00000000
R SPF1_SPF_INT_MASKED 0x0000000B 0x00000000
R SPF1_SPF_MASK_SET 0x0000000B 0x00000000
R SPF1_SPF_MASK_CLR 0x0000000B 0x00000000
R SPF2_SPF_IDVER 0x0000000B 0x00280100
R SPF2_SPF_STATUS 0x0000000B 0x00000000
R SPF2_SPF_CONTROL 0x0000000B 0x00000000
R SPF2_SPF_DROPCOUNT 0x0000000B 0x00000000
R SPF2_SPF_SWRESET 0x0000000B 0x00000000
R SPF2_SPF_PRESCALE 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_0 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_1 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_2 0x0000000B 0x00000000
R SPF2_SPF_RATELIMi_3 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_0 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_1 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_2 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_3 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_4 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_5 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_6 0x0000000B 0x00000000
R SPF2_SPF_CONSTj_7 0x0000000B 0x00000000
R SPF2_SPF_INSTRW2 0x0000000B 0x00000000
R SPF2_SPF_INSTRW1 0x0000000B 0x00000000
R SPF2_SPF_INSTRW0 0x0000000B 0x00000000
R SPF2_SPF_INSTR_CTL 0x0000000B 0x00000000
R SPF2_SPF_LOG_BEGIN 0x0000000B 0x00000000
R SPF2_SPF_LOG_END 0x0000000B 0x00001000
R SPF2_SPF_LOG_HWPTR 0x0000000B 0x00000000
R SPF2_SPF_LOG_SWPTR 0x0000000B 0x00000000
R SPF2_SPF_LOG_MAP0 0x0000000B 0x00000000
R SPF2_SPF_LOG_MAP1 0x0000000B 0x00000000
R SPF2_SPF_LOG_THRESHk_0 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_1 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_2 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_3 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_4 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_5 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_6 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_7 0x0000000B 0x0000000A
R SPF2_SPF_LOG_THRESHk_8 0x0000000B 0x0000000A
R SPF2_SPF_INTCNT 0x0000000B 0x00000001
R SPF2_SPF_INT_RAW 0x0000000B 0x00000000
R SPF2_SPF_INT_MASKED 0x0000000B 0x00000000
R SPF2_SPF_MASK_SET 0x0000000B 0x00000000
R SPF2_SPF_MASK_CLR 0x0000000B 0x00000000
R MDIO_MDIO_VER 0x0000000B 0x40070106
R MDIO_MDIO_CONTROL 0x0000000B 0x41000059
R MDIO_MDIO_ALIVE 0x0000000B 0x00000000
R MDIO_MDIO_LINK 0x0000000B 0x00000000
R MDIO_MDIO_LINKINTRAW 0x0000000B 0x00000000
R MDIO_MDIO_LINKINTMASKED 0x0000000B 0x00000000
R MDIO_MDIO_USERINTRAW 0x0000000B 0x00000000
R MDIO_MDIO_USERINTMASKED 0x0000000B 0x00000000
R MDIO_MDIO_USERINTMASKSET 0x0000000B 0x00000000
R MDIO_MDIO_USERINTMASKCLR 0x0000000B 0x00000000
R MDIO_MDIO_USERACCESS0 0x0000000B 0x00000000
R MDIO_MDIO_USERPHYSEL0 0x0000000B 0x00000000
R MDIO_MDIO_USERACCESS1 0x0000000B 0x00000000
R MDIO_MDIO_USERPHYSEL1 0x0000000B 0x00000000
R STATS_GOOD_RX_FRAMES 0x0000000B 0x0000027C
R STATS_BROADCAST_RX_FRAMES 0x0000000B 0x0000025C
R STATS_MULTICAST_RX_FRAMES 0x0000000B 0x0000001F
R STATS_PAUSE_RX_FRAMES 0x0000000B 0x00000000
R STATS_RX_CRC_ERRORS 0x0000000B 0x00000000
R STATS_RX_ALIGN_CODE_ERRORS 0x0000000B 0x00000000
R STATS_OVERSIZE_RX_FRAMES 0x0000000B 0x00000000
R STATS_RX_JABBERS 0x0000000B 0x00000000
R STATS_UNDERSIZE_RX_FRAMES 0x0000000B 0x00000000
R STATS_RX_FRAGMENTS 0x0000000B 0x00000003
R STATS_RX_OCTETS 0x0000000B 0x0000AAE0
R STATS_GOOD_TX_FRAMES 0x0000000B 0x0000000C
R STATS_BROADCAST_TX_FRAMES 0x0000000B 0x0000000C
R STATS_MULTICAST_TX_FRAMES 0x0000000B 0x00000000
R STATS_PAUSE_TX_FRAMES 0x0000000B 0x00000000
R STATS_DEFERRED_TX_FRAMES 0x0000000B 0x00000000
R STATS_COLLISIONS 0x0000000B 0x00000000
R STATS_SINGLE_COLLISION_TX_FRAMES 0x0000000B 0x00000000
R STATS_MULTIPLE_COLLISION_TX_FRAMES 0x0000000B 0x00000000
R STATS_EXCESSIVE_COLLISIONS 0x0000000B 0x00000000
R STATS_LATE_COLLISIONS 0x0000000B 0x00000000
R STATS_TX_UNDERRUN 0x0000000B 0x00000000
R STATS_CARRIER_SENSE_ERRORS 0x0000000B 0x00000000
R STATS_TX_OCTETS 0x0000000B 0x00000300
R STATS_RX_TX_64_OCTET_FRAMES 0x0000000B 0x00000265
R STATS_RX_TX_65_127_OCTET_FRAMES 0x0000000B 0x00000016
R STATS_RX_TX_128_255_OCTET_FRAMES 0x0000000B 0x0000000A
R STATS_RX_TX_256_511_OCTET_FRAMES 0x0000000B 0x00000002
R STATS_RX_TX_512_1023_OCTET_FRAMES 0x0000000B 0x00000001
R STATS_RX_TX_1024_UP_OCTET_FRAMES 0x0000000B 0x00000000
R STATS_NET_OCTETS 0x0000000B 0x0000AE07
R STATS_RX_START_OF_FRAME_OVERRUNS 0x0000000B 0x00000239
R STATS_RX_MIDDLE_OF_FRAME_OVERRUNS 0x0000000B 0x00000000
R STATS_RX_DMA_OVERRUNS 0x0000000B 0x00000239
R SS_CPSW_ID_VER 0x0000000B 0x0019010F
R SS_CPSW_CONTROL 0x0000000B 0x00000000
R SS_CPSW_SOFT_RESET 0x0000000B 0x00000000
R SS_CPSW_STAT_PORT_EN 0x0000000B 0x00000007
R SS_CPSW_PTYPE 0x0000000B 0x00000000
R SS_CPSW_SOFT_IDLE 0x0000000B 0x00000000
R SS_CPSW_THRU_RATE 0x0000000B 0x00003003
R SS_CPSW_GAP_THRESH 0x0000000B 0x0000000B
R SS_CPSW_TX_START_WDS 0x0000000B 0x00000020
R SS_CPSW_FLOW_CONTROL 0x0000000B 0x00000001
R SS_CPSW_VLAN_LTYPE 0x0000000B 0x81008100
R SS_CPSW_TS_LTYPE 0x0000000B 0x00000000
R SS_CPSW_DLR_LTYPE 0x0000000B 0x000080E1
R SS_CPSW_EEE_PRESCALE 0x0000000B 0x00000000
R STATERAM_TX0_HDP 0x0000000B 0x00000000
R STATERAM_TX1_HDP 0x0000000B 0x00000000
R STATERAM_TX2_HDP 0x0000000B 0x00000000
R STATERAM_TX3_HDP 0x0000000B 0x00000000
R STATERAM_TX4_HDP 0x0000000B 0x00000000
R STATERAM_TX5_HDP 0x0000000B 0x00000000
R STATERAM_TX6_HDP 0x0000000B 0x00000000
R STATERAM_TX7_HDP 0x0000000B 0x00000000
R STATERAM_RX0_HDP 0x0000000B 0x00000000
R STATERAM_RX1_HDP 0x0000000B 0x00000000
R STATERAM_RX2_HDP 0x0000000B 0x00000000
R STATERAM_RX3_HDP 0x0000000B 0x00000000
R STATERAM_RX4_HDP 0x0000000B 0x00000000
R STATERAM_RX5_HDP 0x0000000B 0x00000000
R STATERAM_RX6_HDP 0x0000000B 0x00000000
R STATERAM_RX7_HDP 0x0000000B 0x00000000
R STATERAM_TX0_CP 0x0000000B 0x48486450
R STATERAM_TX1_CP 0x0000000B 0x00000000
R STATERAM_TX2_CP 0x0000000B 0x00000000
R STATERAM_TX3_CP 0x0000000B 0x00000000
R STATERAM_TX4_CP 0x0000000B 0x00000000
R STATERAM_TX5_CP 0x0000000B 0x00000000
R STATERAM_TX6_CP 0x0000000B 0x00000000
R STATERAM_TX7_CP 0x0000000B 0x00000000
R STATERAM_RX0_CP 0x0000000B 0x48486020
R STATERAM_RX1_CP 0x0000000B 0x00000000
R STATERAM_RX2_CP 0x0000000B 0x00000000
R STATERAM_RX3_CP 0x0000000B 0x00000000
R STATERAM_RX4_CP 0x0000000B 0x00000000
R STATERAM_RX5_CP 0x0000000B 0x00000000
R STATERAM_RX6_CP 0x0000000B 0x00000000
R STATERAM_RX7_CP 0x0000000B 0x00000000
R CPTS_CPTS_IDVER 0x0000000B 0x4E8A0105
R CPTS_CPTS_CONTROL 0x0000000B 0x00000005
R CPTS_CPTS_TS_PUSH 0x0000000B 0x00000000
R CPTS_CPTS_TS_LOAD_VAL 0x0000000B 0x00000000
R CPTS_CPTS_TS_LOAD_EN 0x0000000B 0x00000000
R CPTS_CPTS_INTSTAT_RAW 0x0000000B 0x00000001
R CPTS_CPTS_INTSTAT_MASKED 0x0000000B 0x00000001
R CPTS_CPTS_INT_ENABLE 0x0000000B 0x00000001
R CPTS_CPTS_EVENT_POP 0x0000000B 0x00000000
R CPTS_CPTS_EVENT_LOW 0x0000000B 0x00000000
R CPTS_CPTS_EVENT_HIGH 0x0000000B 0x00200000
R ALE_ALE_IDVER 0x0000000B 0x00290104
R ALE_ALE_CONTROL 0x0000000B 0x80000010
R ALE_ALE_PRESCALE 0x0000000B 0x0001E848
R ALE_ALE_UNKNOWN_VLAN 0x0000000B 0x3F06061F
R ALE_ALE_TBLCTL 0x0000000B 0x00000000
R ALE_ALE_TBLW2 0x0000000B 0x00000000
R ALE_ALE_TBLW1 0x0000000B 0x50000CAE
R ALE_ALE_TBLW0 0x0000000B 0x7D115AF6
R ALE_ALE_PORTCTL0 0x0000000B 0x00000003
R ALE_ALE_PORTCTL1 0x0000000B 0x00000003
R ALE_ALE_PORTCTL2 0x0000000B 0x00000003
R ALE_ALE_PORTCTL3 0x0000000B 0x00000000
R ALE_ALE_PORTCTL4 0x0000000B 0x00000000
R ALE_ALE_PORTCTL5 0x0000000B 0x00000000
R SL1_SL_IDVER 0x0000000B 0x00170113
R SL1_SL_MACCONTROL 0x0000000B 0x000200B9
R SL1_SL_MACSTATUS 0x0000000B 0x80000018
R SL1_SL_SOFT_RESET 0x0000000B 0x00000000
R SL1_SL_RX_MAXLEN 0x0000000B 0x000005F2
R SL1_SL_BOFFTEST 0x0000000B 0x01750000
R SL1_SL_RX_PAUSE 0x0000000B 0x00000000
R SL1_SL_TX_PAUSE 0x0000000B 0x00000000
R SL1_SL_EMCONTROL 0x0000000B 0x00000000
R SL1_SL_RX_PRI_MAP 0x0000000B 0x00000000
R SL1_SL_TX_GAP 0x0000000B 0x0000000C
R SL2_SL_IDVER 0x0000000B 0x00170113
R SL2_SL_MACCONTROL 0x0000000B 0x000200B9
R SL2_SL_MACSTATUS 0x0000000B 0x80000000
R SL2_SL_SOFT_RESET 0x0000000B 0x00000000
R SL2_SL_RX_MAXLEN 0x0000000B 0x000005F2
R SL2_SL_BOFFTEST 0x0000000B 0x033E0000
R SL2_SL_RX_PAUSE 0x0000000B 0x00000000
R SL2_SL_TX_PAUSE 0x0000000B 0x00000000
R SL2_SL_EMCONTROL 0x0000000B 0x00000000
R SL2_SL_RX_PRI_MAP 0x0000000B 0x44444444
R SL2_SL_TX_GAP 0x0000000B 0x0000000C
R WR_WR_IDVER 0x0000000B 0x4EDB1902
R WR_WR_SOFT_RESET 0x0000000B 0x00000000
R WR_WR_CONTROL 0x0000000B 0x0000000A
R WR_WR_INT_CONTROL 0x0000000B 0x00030271
R WR_WR_C0_RX_THRESH_EN 0x0000000B 0x00000001
R WR_WR_C0_RX_EN 0x0000000B 0x00000001
R WR_WR_C0_TX_EN 0x0000000B 0x00000001
R WR_WR_C0_MISC_EN 0x0000000B 0x0000001C
R WR_WR_C0_RX_THRESH_STAT 0x0000000B 0x00000001
R WR_WR_C0_RX_STAT 0x0000000B 0x00000001
R WR_WR_C0_TX_STAT 0x0000000B 0x00000000
R WR_WR_C0_MISC_STAT 0x0000000B 0x00000010
R WR_WR_C0_RX_IMAX 0x0000000B 0x00000002
R WR_WR_C0_TX_IMAX 0x0000000B 0x00000002
R WR_WR_RGMII_CTL 0x0000000B 0x0000000D
R WR_WR_STATUS 0x0000000B 0x00000006
R CPDMA_CPDMA_TX_IDVER 0x0000000B 0x00180109
R CPDMA_CPDMA_TX_CONTROL 0x0000000B 0x00000001
R CPDMA_CPDMA_TX_TEARDOWN 0x0000000B 0x00000000
R CPDMA_CPDMA_RX_IDVER 0x0000000B 0x00180109
R CPDMA_CPDMA_RX_CONTROL 0x0000000B 0x00000001
R CPDMA_CPDMA_RX_TEARDOWN 0x0000000B 0x00000000
R CPDMA_CPDMA_SOFT_RESET 0x0000000B 0x00000000
R CPDMA_CPDMA_DMACONTROL 0x0000000B 0x00000000
R CPDMA_CPDMA_DMASTATUS 0x0000000B 0x80000000
R CPDMA_CPDMA_RX_BUFFER_OFFSET 0x0000000B 0x00000000
R CPDMA_CPDMA_EMCONTROL 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI0_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI1_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI2_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI3_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI4_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI5_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI6_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_PRI7_RATE 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_INTSTAT_RAW 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_INTSTAT_MASKED 0x0000000B 0x00000000
R CPDMA_CPDMA_TX_INTMASK_SET 0x0000000B 0x00000001
R CPDMA_CPDMA_TX_INTMASK_CLEAR 0x0000000B 0x00000001
R CPDMA_CPDMA_IN_VECTOR 0x0000000B 0x10000101
R CPDMA_CPDMA_EOI_VECTOR 0x0000000B 0x00000001
R CPDMA_CPDMA_RX_INTSTAT_RAW 0x0000000B 0x00000101
R CPDMA_CPDMA_RX_INTSTAT_MASKED 0x0000000B 0x00000101
R CPDMA_CPDMA_RX_INTMASK_SET 0x0000000B 0x00000101
R CPDMA_CPDMA_RX_INTMASK_CLEAR 0x0000000B 0x00000101
R CPDMA_CPDMA_DMA_INTSTAT_RAW 0x0000000B 0x00000000
R CPDMA_CPDMA_DMA_INTSTAT_MASKED 0x0000000B 0x00000000
R CPDMA_CPDMA_DMA_INTMASK_SET 0x0000000B 0x00000003
R CPDMA_CPDMA_DMA_INTMASK_CLEAR 0x0000000B 0x00000003
R CPDMA_CPDMA_RX0_PENDTHRESH 0x0000000B 0x00000010
R CPDMA_CPDMA_RX1_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX2_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX3_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX4_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX5_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX6_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX7_PENDTHRESH 0x0000000B 0x00000000
R CPDMA_CPDMA_RX0_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX1_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX2_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX3_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX4_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX5_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX6_FREEBUFFER 0x0000000B 0x00000000
R CPDMA_CPDMA_RX7_FREEBUFFER 0x0000000B 0x00000000
R PORT_P0_CONTROL 0x0000000B 0x00000000
R PORT_P0_MAX_BLKS 0x0000000B 0x00000104
R PORT_P0_BLK_CNT 0x0000000B 0x00000042
R PORT_P0_TX_IN_CTL 0x0000000B 0x000040C0
R PORT_P0_PORT_VLAN 0x0000000B 0x00000000
R PORT_P0_TX_PRI_MAP 0x0000000B 0x00030003
R PORT_P0_CPDMA_TX_PRI_MAP 0x0000000B 0x76543210
R PORT_P0_CPDMA_RX_CH_MAP 0x0000000B 0x07770777
R PORT_P0_RX_DSCP_PRI_MAP0 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP1 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP2 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP3 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP4 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP5 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP6 0x0000000B 0x00000000
R PORT_P0_RX_DSCP_PRI_MAP7 0x0000000B 0x00000000
R PORT_P0_IDLE2LPI 0x0000000B 0x00000000
R PORT_P0_LPI2WAKE 0x0000000B 0x00000000
R PORT_P1_CONTROL 0x0000000B 0x00000000
R PORT_P1_MAX_BLKS 0x0000000B 0x00000113
R PORT_P1_BLK_CNT 0x0000000B 0x00000042
R PORT_P1_TX_IN_CTL 0x0000000B 0x080040C0
R PORT_P1_PORT_VLAN 0x0000000B 0x00000001
R PORT_P1_TX_PRI_MAP 0x0000000B 0x33221001
R PORT_P1_TS_SEQ_MTYPE 0x0000000B 0x001E0000
R PORT_P1_SA_LO 0x0000000B 0x0000F65A
R PORT_P1_SA_HI 0x0000000B 0x117DAE0C
R PORT_P1_SEND_PERCENT 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP0 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP1 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP2 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP3 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP4 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP5 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP6 0x0000000B 0x00000000
R PORT_P1_RX_DSCP_PRI_MAP7 0x0000000B 0x00000000
R PORT_P1_IDLE2LPI 0x0000000B 0x00000000
R PORT_P1_LPI2WAKE 0x0000000B 0x00000000
R PORT_P2_CONTROL 0x0000000B 0x00000000
R PORT_P2_MAX_BLKS 0x0000000B 0x00000113
R PORT_P2_BLK_CNT 0x0000000B 0x00000041
R PORT_P2_TX_IN_CTL 0x0000000B 0x080040C0
R PORT_P2_PORT_VLAN 0x0000000B 0x00000001
R PORT_P2_TX_PRI_MAP 0x0000000B 0x33221001
R PORT_P2_TS_SEQ_MTYPE 0x0000000B 0x001E0000
R PORT_P2_SA_LO 0x0000000B 0x0000F75A
R PORT_P2_SA_HI 0x0000000B 0x117DAE0C
R PORT_P2_SEND_PERCENT 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP0 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP1 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP2 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP3 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP4 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP5 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP6 0x0000000B 0x00000000
R PORT_P2_RX_DSCP_PRI_MAP7 0x0000000B 0x00000000
R PORT_P2_IDLE2LPI 0x0000000B 0x00000000
R PORT_P2_LPI2WAKE 0x0000000B 0x00000000

NDK_conf.cfg

0 Prasad Jondhale over 6 years ago in reply to tejeswini jayaram

TI__Mastermind 27743 points

Hello Tejeswini,

Thanks for detailed summary. As planned, we can debug this in WebEx session and confirm if any issues on the link side.

0 Prasad Jondhale over 6 years ago in reply to Prasad Jondhale

TI__Mastermind 27743 points

Closing this thread as debug happening via mail.

Processors

Processors forum

TDA2PXEVM: PHY_ALIVE signal with a switch between PHY and TDA2px