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RTOS/AM5728: shared data memory block(SBL, Application, Host by pci-e)

soonisys
Prodigy 250 points
Part Number: AM5728

Tool/software: TI-RTOS

Hello, I'm a very newbie on AM5728.

I'm using IDK5728 for new project.(we will make a custom board after firmware test)

I have one data memory block(such as one large array or structure which is about 100MB).

I'd like to share this data memory between SBL, Application and Host(pci-e).

The idk5728 work as pci-e end point.(The custome board will be pci-e card)

My application will do many things with this data memory block.(calculate, read/write). 

Actually, this memory block is almost main data memory for application.

Host will access this data memory very often by pci-e.

So, speed is important.

So, I think my boot-up sequence should be like this...

=Requirement is..

1. I have to initialize pci-e ASAP.(in 100~200ms from power up)

2. SBL, application, host PC need to access one big data memory block(one big structure-100MB)

3. This data memory is on DDR memory(emif)

=Question is...

1. Is this boot-up sequence correct?

2. How to declare this data memory block on specific memory address?

3. When should I declare this data memory block?

4. Should I initialize pci-e in my application again?( I guess I should)

5. Is there a better way to do this?

Please...help me~~~~~!!!

Thank you and have a nice day!!

  • 0
    TI__Guru** 116170 points
    Few questions here:

    What is the boot media that you are booting from, is it QSPI flash of MMCSD ? Is the need to allocate MEmory buffer and establish PCIe connection essentially so your card gets detected as soon as possible.

    I would like you to look at the training for designing quick boot and also look at slide 42 in detail to get some estimate.
    training.ti.com/.../Design-Quick-Start-Embedded-Systems-SLIDES.pdf

    With QSPI boot at 48 Mhz, you will be much faster than SD/MMC and should be able to meet the 200 ms requirement so you should look to pick the faster boot media. I am also not sure why you need the allocation of the buffer and PCIe init to be part of SBL. You should make the SBL as small as possible and remove all un wanted functionality and pass control to your application as soon as possible. The SBL doesn`t exist once the application has booted up so not sure there is any message exchange between app and SBL and Host possible at any instance.

    your boot time requirement will also depend on how quickly, you can have the PCIe establish a link with the host. I will loop in our PCIE expert to comment on how this can be done. In the meantime, you can checkout PCIE test examples, the driver examples:

    software-dl.ti.com/.../Device_Drivers.html
    and CSL example
    pdk_am65xx_1_0_2\packages\ti\csl\example\pcie\write_loopback

    (Check for inbound and outbound PCIE address and region definition)

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Prodigy 250 points

    Thank you for your answer. It's really fast answer!!!! Thanks a lot.

    I'm planning to use 8bit bus NOR flash for boot device. Because I think XIP boot is the fastest.

    The thing is I can not check with my IDK5728.

    *** I checked boot up time by SPI NOR flash with my idk5728. It was about 280ms from hard reset until the SBL initializes a board.

    The reason why I want fast boot is only pci-e card detection problem by host PC.

    In my opinion, the SBL has to initialize pci-e as fast as possible to be detected by host.

    My application is not very small. If I initialize pci-e in my application, it will be too late.

    And I think I need information about inbound and outbound address when I initialize pci-e...

    That's why I want to allocate shared data memory buf in SBL.

    Actually, the SBL will not use shared data memory buf which I'd like to allocate for application. It is only for application and host(pci-e)

    But the thing is I'm not sure about pci-e init and memory address for pci-e, so I have to check the examples again.

    If my scenario about memory for pci-e is not correct, then I don't need memory buf in SBL.

    I'll just allocate memory buf in the application and it will be easier...

    BTW, the host has to upload application image by pci-e at first.

    Because NOR flash will not have application image from factory product.

    We will write only SBL in factory...so I think I need pci-e stuff in SBL or I need another application for upload/download main application image...

    We don't want to write main application in flash. but it's okay for other application such as app for up/download.

    What is your suggestion for this.??

    idea1. SBL take care about main application download from host by pci-e.

    idea2. SBL load upload/download application from flash if there is no main application.

    Thanks a lot for your kindness and supports.

    p.s:Plz don't feel bad with my horrible english...

  • 0 in reply to soonisys
    TI__Guru* 95265 points
    Hi,

    For the PCIE part, several things I want to check with you:
    1) Is correct the PCIE host is a PC? Linux? Windows?
    2) If it is a PC, do you have a PCIE driver for that?
    3) The PCIE EP is your own board, not TI AM5728x EVM, correct? And it has the capability to use the PCIE reference clock from host?
    4) Are you able to successfully enumerate your AM572x board by your host?
    5) The Processor SDK RTOS PCIE driver we have used hard-coded inbound and outbound addresses because this is board-to-board test. That is, a static configuration without enumeration process, we just do link training.
    6) If you do the enumeration from host, the PCIE EP side you can only setup BAR mask, the memory allocated inside PCIE host is dynamic. Your need have a PCIE driver on your host side, it reads out the assigned memory address and the host PCIE driver needs to program this into PCIE EP side inbound translation.
    7) In the past, we have such PCIE driver example on Linux host for an earlier DSP chip. And the DSP chip also has a SBL, we do PCIE initialization inside SBL. After the enumeration, the host download image to the EP and lets EP start to run. The SBL is boot from I2C bus (speed is very slow). Certainly if the SBL is too slow, you will miss the host enumeration time window. But it is not necessarily you want to the SBL run as fast as possible, we found that many host machines issue a host reset after the enumeration, so the PCIE link gets lost in this case. We need to control that the time where PCIE init runs, not too early, not too late.

    You can either do PCIE init inside SBL, or using SBL to load a small application to initialize PCIE. After that, using the PCIE to download your real big application into EP and starts to run.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 250 points

    Thank you for your answer.
    =========================================================
    Here are answers and some questions for your check list:
    1) PCIE host is PC(windows)
    2) Another team is working for pcie driver on Windows...
    3) The PCIE EP will be our own board, but I need to test with idk5728.
    =========================================================
    What host does is...
    If there is no application in flash, SBL will wait for host download real application.
    The host will download real application into DDR RAM area and board will copy it into flash.
    Then, after reset, board will load application from flash by itself, if there is right application in flash.
    *A host download application when only there is update version.
    A host always read/write memory while real application is running.(The application does as well)
    ==========================================================
    Question after your advice....:
    Q.1) Is it possible to test pcie ep with idk5782, if I have a driver? We will design pci-e hardware part just same as idk5728's.
    Q.2) SBL and application use pci-e. So, should I reinitialize pci-e in my real application even though SBL already initialized?
    Q.3) What parameters should I give to host driver team? (frankly speaking, this is what I need for now...)

    I love to wait for your answer. Thank you!

  • 0 in reply to soonisys
    TI__Guru* 95265 points
    Hi,

    For Q1: Please check this link: e2e.ti.com/.../653443
    For Q2: No, you just need initialize it once.
    For Q3, we don't have any Linux or windows driver for AM57x PCIE, so I can't comment this specifically. In general, the EP side need to configured to accept the PCIE reference clock from PCIE host. Also, you need configure the BAR mask for the host to allocate memory.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 250 points
    Thank you so much for your answer.
    It helps me a lot.
    I love TI!!!!