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Original question:

Dm6437 MACstatus "Ownership bit not set in SOP buffer",

CCS/TMS320C6746: c6746 MACstatus "Ownership bit not set in SOP buffer",

VISHNUVARDHAN VATTE
Intellectual 430 points
Part Number: TMS320C6746

Tool/software: Code Composer Studio

hii

I wrote a code for ethernet physical layer through which I can send some packets from my dsp(c6746) to someother dsp. I am checking for ethernet packets on my pc using wireshark software. When I debug my code and check in macstatus register I am getting "Ownership bit not set in SOP buffer" error sometimes and "SOP bit not set by software" error sometimes. But I have actually set both those bits in software and while debugging I can see that those bits were set. 

  • 0
    TI__Guru**** 161600 points
    Hi,

    Do you use the NDK apis or is this a pure bare metal application? Is this a custom board or reference TI EVM? If you use custom board, how does it differ from TI EVM?
    Which Processor SDK RTOS version are you using, if any? Which CCS version?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru**** 161600 points
    Hi,

    I haven't heard back. Closing this thread for now. You can reopen it by posting the required information.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 430 points

    HI Yordan,

    This is a pure bare metal application. It is a TI EVM board(TMS320C6746). I am not using any SDK . The ccs version I'm using is version 7.

    Regards,
    Vishnu

  • 0 in reply to VISHNUVARDHAN VATTE
    Intellectual 430 points
    sorry I'm using a custom board on which TMS320C6746 is mounted
  • 0 in reply to VISHNUVARDHAN VATTE
    TI__Mastermind 27355 points

    Hello,

    Similar issues were discussed in the following threads. Please see if they help resolve your issue if you have not done so already.

    As mentioned in one of the other threads, since this happens only sometimes, it may indicate a timing issue/race condition. 

    Where are you storing your packet buffers? If it's in cacheable memory, please see this snippet from the driver:

    In systems where the packet resides in cacheable memory, the data buffer
 *  must start on a cache line boundary and be an even multiple of cache
 *  lines in size. The EMAC_Pkt header must not appear in the same cache line
 *  as the data portion of the packet. On multi-fragment packets, some packet
 *  fragments may reside in cacheable memory where others do not.
 *
 *  
    NOTE: It is up to the caller to assure that all packet buffers
    residing in cacheable memory are not currently stored in L1 or L2
    cache when passed to any EMAC function.

  • 0 in reply to Sahin Okur
    Intellectual 430 points

    Hi

    I have gone through the above links and tried most of them but still my problem is not resolved. I even tried storing my descriptors and buffer data in sdram but it didn't work. I am still getting the "OWNERSHIP BIT NOT SET" error. Whenever i'm moving my first descriptor to TX0HDP the ownership bit of my first descriptor is clearing automatically(which also indicates that the EMAC has processed all descriptors in my current packet but it is also giving OWNERSHIP error).  I would also like to know the base address for cppi ram. I assumed it as 0x02c82000 and when i store my first descriptor there then i'm getting NULL ERROR in TXERROR code and it is changed to SOP error when I do memory allocation using malloc function for my descriptor. If I store my descriptors in sdram or L2 cache i need not do any memory allocation using malloc but still getting  OWNERSHIP error.Could you help me with this.(i am trying to send 6 packets each packet having one fragment)

    Regards
    Vishnu

  • 0 in reply to Sahin Okur
    Intellectual 430 points
    Hi

    I have gone through the above links and tried most of them but still my problem is not resolved. I even tried storing my descriptors and buffer data in sdram but it didn't work. I am still getting the "OWNERSHIP BIT NOT SET" error. Whenever i'm moving my first descriptor to TX0HDP the ownership bit of my first descriptor is clearing automatically(which also indicates that the EMAC has processed all descriptors in my current packet but it is also giving OWNERSHIP error). I would also like to know the base address for cppi ram. I assumed it as 0x02c82000 and when i store my first descriptor there then i'm getting NULL ERROR in TXERROR code and it is changed to SOP error when I do memory allocation using malloc function for my descriptor. If I store my descriptors in sdram or L2 cache i need not do any memory allocation using malloc but still getting OWNERSHIP error.Could you help me with this.(i am trying to send 6 packets each packet having one fragment)

    Regards
    Vishnu