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Original question:

CCS/CCSTUDIO: path inclusion problems

TMS320C6748: Which Clock source to use and which SDRAM and EMAC frequency to set when generating the application image script?

Juan Encinas
Intellectual 510 points
Part Number: TMS320C6748

Hi,

I was wondering if you could tell me which clock source sould i mark and with which frequency as well as which is the recommended frequency to set to the SDRAM and EMAC(I don't know even what EMAC Stands for) on the PLL0 and why?

Thanks in advace,

Juan

  • 0
    TI__Guru**** 161600 points
    Hi,

    Just wanted to let you know that this is forwarded to the appropriate experts, but there may be delay in the answer due to holidays in the US.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 29560 points

    Hi Juan,

    I'm assuming you mean the SDRAM external memory interface (EMIFA), and not the DDR2/MDDR controller.

    In the TMS320C6748 datasheet, Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point.
    100 MHz for 1.3V NOM
    50 MHz for 1.0V NOM

    The same information is also presented in Table 6-20. Switching Characteristics for EMIFA SDRAM Interface

    So the maximum SDRAM CLK frequency supported by the C6748 is 100MHz.
    You must also not surpass the frequency of the SDRAM itself.

    There is no SDRAM on the C6748 LCDK DEV Kit or the obsoleted Logic PD Experimenter board. What is the SDRAM you had in mind?

    You might want to maximize the CPU frequency (456MHz) and then get the fastest SDRAM frequency allowable by the device and your SDRAM. Same goes for EMAC.

    Or you might want to run the CPU slower, but with maximum SDRAM frequency.


    EMAC refers to the 10/100 Mbps Ethernet media access controller (EMAC)
    The AISGen tool will flag an error if the EMAC clock is set faster than 50MHz.
    That requirement corresponds to the Optional 50 MHz clock source for EMAC RMII interface in Table 6-5. This 50MHz refclk can also be input externally through the RMII_MHZ_50_CLK pin..

    50 MHz is also presented in Table 6-102. Timing Requirements for EMAC RMII - min tc(REFCLK) = 20ns (1/50MHz)

    See also these E2E questions:
    e2e.ti.com/.../418505
    e2e.ti.com/.../215698

    And these wiki pages:
    processors.wiki.ti.com/.../OMAPL138_StarterWare_Booting_And_Flashing
    processors.wiki.ti.com/.../OMAP-L138_Software_Design_Guide
    processors.wiki.ti.com/.../OMAP-L138_Bootloader

    And this app note:
    Using the TMS320C6748/C6746/C6742 Bootloader (Rev. F) www.ti.com/.../spraat2

    Hope this helps.

    Regards,
    Mark