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Linux/AM3359: External PHY with RGMII of AM3359 Procerrsor

Part Number: AM3359

Tool/software: Linux

Hello,

I have connected Marvel Alaska 88E1510 PHY with AM3359 processor's RGMII port for establishing 1Gbps Ethernet communication.

Kindly share the device tree configuration for the same.

Whether I have to do the inclusion in device tree alone or kernel anything need to be configure ?

thanks

Mobin P K

  • Hi,

    Please note that due to US holiday the responses may be delayed until the week of November 26th.
  • Sir,

    Waiting for your response

    thanks
    Mobin P K
  • Hi,

    For this answer I will assume that you are using the latest TI Processors Linux SDK. Please take a look at this file located in the kernel source tree arch/arm/boot/dts/am335x-evmsk.dts. The nodes mac, davinci_mdio, cpsw_emac0 and cpsw_emac1 are configuring two ethernet interfaces for RGMII. This should probably work for your board, be sure to verify the pin mux structure called out in the mac structure matches the interface pins your board. Please note that the phy_id element in the emac nodes will need to be set to the phy addresses on your board.

    Best Regards,
    Schuyler
  • thanks for your reply.

    where can I find the phy address for setting the PHY ID ?

    thanks
    Mobin P K
  • Hi,
    The only answer I have is to ask the HW designer of the board, they set the PHY addressing and the HW configuration settings of the PHY.
    Best Regards,
    Schuyler
  • Hello,

    Kindly share any reference device tree configuration for the same.

    thanks
    Mobin P K
  • Hi,

    From the earlier post in this thread this contains the example you need:

    Please take a look at this file located in the kernel source tree arch/arm/boot/dts/am335x-evmsk.dts. The nodes mac, davinci_mdio, cpsw_emac0 and cpsw_emac1 are configuring two ethernet interfaces for RGMII. This should probably work for your board, be sure to verify the pin mux structure called out in the mac structure matches the interface pins your board. Please note that the phy_id element in the emac nodes will need to be set to the phy addresses on your board.

    The PHY addresses are going to be on the HW schematic. The HW designer of the board will be able to tell you what the address of the PHY was strapped or configured for. The addressing is typically set with resistors and the PHY datasheet will describe this configuration step.

    Best Regards,
    Schuyler
  • Sir,


    I have updated the device tree with following changes

    am33xx.dtsi

    /************************************************************/

    / {
    compatible = "ti,am33xx";
    interrupt-parent = <&intc>;

    aliases {
    i2c0 = &i2c0;
    i2c1 = &i2c1;
    i2c2 = &i2c2;
    serial0 = &uart0;
    serial1 = &uart1;
    serial2 = &uart2;
    serial3 = &uart3;
    serial4 = &uart4;
    serial5 = &uart5;
    d_can0 = &dcan0;
    d_can1 = &dcan1;
    usb0 = &usb0;
    usb1 = &usb1;
    phy0 = &usb0_phy;
    phy1 = &usb1_phy;
    ethernet0 = &cpsw_emac0;
    ethernet1 = &cpsw_emac1;
    };

    mac: ethernet@4a100000 {
    compatible = "ti,am335x-cpsw","ti,cpsw";
    ti,hwmods = "cpgmac0";
    clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
    clock-names = "fck", "cpts";
    cpdma_channels = <8>;
    ale_entries = <1024>;
    bd_ram_size = <0x2000>;
    no_bd_ram = <0>;
    mac_control = <0x20>;
    slaves = <2>;
    active_slave = <0>;
    cpts_clock_mult = <0x80000000>;
    cpts_clock_shift = <29>;
    reg = <0x4a100000 0x800
    0x4a101200 0x100>;
    #address-cells = <1>;
    #size-cells = <1>;
    interrupt-parent = <&intc>;
    /*
    * c0_rx_thresh_pend
    * c0_rx_pend
    * c0_tx_pend
    * c0_misc_pend
    */
    interrupts = <40 41 42 43>;
    ranges;
    syscon = <&scm_conf>;
    status = "disabled";

    davinci_mdio: mdio@4a101000 {
    compatible = "ti,cpsw-mdio";
    #address-cells = <1>;
    #size-cells = <0>;
    ti,hwmods = "davinci_mdio";
    bus_freq = <1000000>;
    reg = <0x4a101000 0x100>;
    status = "disabled";
    };


    cpsw_emac0: slave@4a100200 {
    /* Filled in by U-Boot */
    mac-address = [ 00 00 00 00 00 00 ];
    };

    cpsw_emac1: slave@4a100300 {

    /* Filled in by U-Boot */
    mac-address = [ 00 00 00 00 00 00 ];
    };



    phy_sel: cpsw-phy-sel@44e10650 {
    compatible = "ti,am3352-cpsw-phy-sel";
    reg= <0x44e10650 0x4>;
    reg-names = "gmii-sel";
    };
    };


    /************************************************************/

    And this is my custom board dtsi

    /************************************************************/

    /* Ethernet */
    &am33xx_pinmux {
    ethernet1_pins: pinmux_ethernet1 {
    pinctrl-single,pins = <

    0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
    0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
    0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
    0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
    0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
    0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
    0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
    0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
    0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
    0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
    0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
    0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
    >;
    };
    };

    &cpsw_emac1 {

    phy_id = <&davinci_mdio>, <0>;

             phy-mode = "rgmii";
             compatible = "marvell,88E1510";


    status = "okay";
    };

    Boot Screen Log is given below, for ethernet 1 also LAN8710 driver is loading but I have include Marvell 88E1510 driver. what are the modification I have to include in my device tree for establishing 1 Gpbs ethernet with RGMII2 & Marvell 88E1510 PHY. PHY address is 0.

    [    1.305719] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
    [    1.312148] davinci_mdio 4a101000.mdio: detected phy mask fffffffc
    [    1.320481] libphy: 4a101000.mdio: probed
    [    1.324693] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
    [    1.334306] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver SMSC LAN8710/LAN8720
    [    1.345254] cpsw 4a100000.ethernet: Detected MACID = 7c:01:0a:a1:f5:a5

    thanks

    Mobin

  • Hi,

    Thanks for posting the dtsi that you are using. I would recommend though that the changes are done to the DTS file rather than the dtsi. Making changes to the dtsi file could create conflicts if you choose to upgrade SDKs later.

    This is a section of code that you can reference from the arch/arm/boot/dts/am335x-evmsk.dts, this is configuration used for the TI EVM SK kit that is sold by TI. Since the board is using PHY addresses 0 and 1 this section of code could be used directly. Please note that the phy-mode field in the emac nodes must be set to rgmii-txid, rgmii most likely will not work. This is due a timing issue in the AM335x. Also please note that the EVM-SK board from TI is using a pin-mux entry called cpsw-default that is defined in the referenced file above.

    This example is using dual mac mode, this means you will see an eth0 and eth1 when using the ifconfig command. If you want switch mode then you will delete the dual_mac field in the mac node.

    The compatible field will not set the driver used, when the PHY Identifier is returned from an mdio transaction there will be a search of available drivers that the kernel has been configured for. Why are you trying to use a different manufacturer's PHY driver than what is installed on the board?

    Which SDK are you using? How did you generate the pin mux settings?

    &mac {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&cpsw_default>;
    pinctrl-1 = <&cpsw_sleep>;
    dual_emac = <1>;
    status = "okay";
    };

    &davinci_mdio {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&davinci_mdio_default>;
    pinctrl-1 = <&davinci_mdio_sleep>;
    status = "okay";
    };

    &cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rgmii-txid";
    dual_emac_res_vlan = <1>;
    };

    &cpsw_emac1 {
    phy_id = <&davinci_mdio>, <1>;
    phy-mode = "rgmii-txid";
    dual_emac_res_vlan = <2>;
    };


    Best Regards,
    Schuyler
  • Hello,

    I am using custom AM3359 board with external Marvell PHY for establishing 1Gbps Ethernet.

    Pin Mux configuration is generated from TI Cloud Tool.


    thanks
    Mobin
  • Hi,

    There looks to be a mis-match on information being presented here. You are saying that you are using one vendor's PHY , but another vendor's PHY is being identified in the boot log:
    [ 1.324693] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
    [ 1.334306] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver SMSC LAN8710/LAN8720

    The PHY that is being identified is a 10/100 PHY and not a 1Gbps PHY. Could you please attach the portion of the schematic showing all of the ethernet connections on your board?

    Also please indicate which TI SDK that is being used here and please attach a file that contains the full boot log.

    Best Regards,
    Schuyler
  • Hi,
    Since we have not heard back we will assume that this issue is resolved and will close the thread for now.
    Best Regards,
    Schuyler