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Original question:

66AK2H12: About K2H PLL

66AK2H12: Register setting INTERNAL CLOCK DIVIDER(S) and SHARED LOCAL CLOCK DIVIDER

Sh.Sasaki
Guru 13625 points
Part Number: 66AK2H12


Hi everyone,

I read DS, but I didn't know which one of the registers to set INTERNAL CLOCK DIVIDER(S) and SHARED LOCAL CLOCK DIVIDER below.

For example, which register sets the ARM CorePac /3 above?
Which register sets PSC's /12 ?]

Best regards,
Sasaki

  • 0
    TI__Mastermind 42545 points
    Hi Sasaki,
    You have misinterpreted the table. The internal clock dividers are not selected using registers. Each of the internal clock dividers is available inside the part and is used by different portions. The table is just showing which of the internal clock dividers are used by which subsystems. For example, the SYSCLK1 /4 is used by COREPACs and the PCIE subsystems. These clocks are based on the frequency programmed into the main PLL.
    Regards, Bill
  • 0 in reply to Bill Taboada
    TI__Mastermind 46460 points

    Sasaki,

    To be clear, the dividers listed in the table that you posted are not programmable.

    Tom

  • 0 in reply to Bill Taboada
    Guru 13625 points

    Hi Bill-san,Tom-san

    Thank you for your support.

    I understood the dividers listed in the table are not programmable.

    Bill Taboada said:
     These clocks are based on the frequency programmed into the main PLL.

    How can I check the  Main PLL's frequency and the division setting to be selected?

    For example, PCIe has four divisions.
    But I do not know which division is selected.

    Best regards,

    Sasaki

  • 0 in reply to Sh.Sasaki
    TI__Mastermind 42545 points

    Hi Sasaki-san,

    The table does not show that clocks that can be selected. The table shows which clocks are created for each of the subsystems. As you pointed out, there are four different clock dividers associated with PCIE. All four of those clocks are created and are provided to the PCIE subsystem for it's use. You can check the frequency of the main PLL using the sysclkout pin. When enabled, this pin should drive the frequency of the main PLL divided by 6.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 13625 points
    Hi Bill-san,

    Thank you for your support.
    I got it.
    Also, thank you for SYSCLKOUT. I learned a lot.

    Best regards,
    Sasaki