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Linux/AM5728: PCIe device tree configuration

Part Number: AM5728


Tool/software: Linux

Hi,

We are developing a custom board based on AM5728 EVM.  we want to utilize  2x lanes from PCIe_SS1  in RC mode.

we have modified the device tree as below

Changes in dra7.dtsi =====================>


        axi@0 {
            compatible = "simple-bus";
            #size-cells = <1>;
            #address-cells = <1>;
            ranges = <0x51000000 0x51000000 0x3000
                  0x0         0x20000000 0x10000000>;
            /**
             * To enable PCI endpoint mode, disable the pcie1_rc
             * node and enable pcie1_ep mode.
             */
            pcie1_rc: pcie_rc@51000000 {
                compatible = "ti,dra7-pcie";
                reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
                reg-names = "rc_dbics", "ti_conf", "config";
                interrupts = <0 232 0x4>, <0 233 0x4>;
                #address-cells = <3>;
                #size-cells = <2>;
                device_type = "pci";
                ranges = <0x81000000 0 0          0x03000 0 0x00010000
                      0x82000000 0 0x20013000 0x13000 0 0xffed000>;
                #interrupt-cells = <1>;
                num-lanes = <2>;
                linux,pci-domain = <0>;
                ti,hwmods = "pcie1";
                phys = <&pcie1_phy>,<&pcie2_phy>;
                phy-names = "pcie-phy0","pcie-phy1";
                interrupt-map-mask = <0 0 0 7>;
                interrupt-map = <0 0 0 1 &pcie1_intc 1>,
                        <0 0 0 2 &pcie1_intc 2>,
                        <0 0 0 3 &pcie1_intc 3>,
                        <0 0 0 4 &pcie1_intc 4>;
                /*status = "disabled";*/
                pcie1_intc: interrupt-controller {
                    interrupt-controller;
                    #address-cells = <0>;
                    #interrupt-cells = <1>;
                };
            };



changes in am57xx-evm-common.dts =======>
&pcie1_rc {
    status = "okay";
    /*gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;*/
};

Please suggest if any additional changes  are required.  Also, help us on how to test the RC with pci_endpoint_test.c 

Best regards,

Marka

  • Hi, Marka,

    Please refer to the AM5728 TRM, PCIe_SS1 can operate in dual-lane mode. You should need to modify the num-lanes only.

    Rex
  • Hi , Rex,
    As per TRM when PCIe_SS1 operates in dual-lane mode , it will make use of pcie2 phy also and pcie2_ss is not available.
    So, we changes num-lanes to 2 and included pcie2_phy to phys property. Please correct if we are wrong

    Marka
  • Hi, Marka,

    Just curious that were you able to enumerate the EP and get a link up? I don't think you need to remove the gpio entry, but you do need to enable pcie2_phy if you haven't.

    Rex
  • Hi Rex,
    we are unable to enumerate EP device. Are these gpio s necessary for enumeration? please explain?
  • Hi, Marka,

    The GPIO is not needed for enumeration, but for reset. On TI EVM, it requires this GPIO, but it may not needed on your board. It depends on your hardware. Are you able to get even just 1 lane configuration up? If not, it's something else.

    Rex
  • Hi, Marka,

    Are you able to get 1 lane configuration up? You should be able to get the EP enumerated with 1-lane configuration. The 2-lane configuation looks good to me except in your original changes, the pcie2_phy wasn't enabled. At this moment without being able to verify 1-lane configuration, I am not sure if it is hardware related. I'll close the issue for now. Once you have 1-lane confguration enumerated and still have issue with 2-lane, please submit a new thread in the forum.

    Thanks!

    Rex
  • Part Number: AM5728

    Tool/software: Linux

    Hi

    we are developing a custom board based on AM5728 GP EVM. we are using two PCie subsystems in x1 configuration. we connected  an endpoint to each PCIe subsystem. But unable to EP detected.

    When we changed the device tree to disable pcie_rc and enable pcie_ep, the endpoints are detected. (Even though we intended to use PCIe subsystems as rootcomplex and attached devices as endpoint)

    what is the correct way to configure device tree if we want to use PCIe subsystems as rootcomplex and attached devices as endpoint. please help us

    Best regards,

    Marka reddy

  • Hi, Marka,

    Please refer to the thread for info, e2e.ti.com/.../764228

    Rex