• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 101 subscribers
  • Views 253 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

[C6655] checking power up/down sequencing

TMS320C6655: Ramp-up timing

Sympson
Intellectual 430 points
Part Number: TMS320C6655

Hi, expert,

I'd like to get confirmation regarding supply ramp up (core before IO) as like this :

According to EVM design, it use FPGA to control ramp up sequence and reset signals by using 5 ms delay between state transition. In some E2E discusion, some design use 8 ms or 11 ms delays. But I did not find the timing specification for this in the datasheet except 100 us + 16 us delay before releasing PORn for the time of device initialization phase. Is there any special reasion to use several miliseconds delay in every state transition ?

Regard,

Sympson

  • 0
    TI__Guru**** 161600 points
    Hi,

    You can have a look at the NOTES after Figure 6-1. Core-Before-IO Power Sequencing in Table 6-2. Core-Before-IO Power Sequencing:
    "RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven high."
    "POR must continue to remain low for at least 100 μs after power has stabilized. End Power Stabilization Phase"
    "RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level."

    So there is a timing requirement for RESETFUL & POR. There is no specific recommendation for a minimum timing between RESET & POR.

    I'd suggest reusing the EVM delays.

    Best Regards,
    Yordan