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Original question:

RTOS: Offset of few horizontal lines are observed before the start of frame.

RTOS: Why there is an offset of 1 or 2 pixels in all vertical lines at the start of row?

jeyaseelan kirubaharan
Expert 1330 points

Tool/software: TI-RTOS

Hi Brijesh,

Thanks for the previous answer . For time being we have adjusted the Display buffer start area to the start of valid frame to resolve the first few blanking periods.I have two more questions as well.Please a

1. Also we have 1 or 2 pixel offset for every vertical lines.What could be the reason for the same?

Have another question on the image quality of frame .

2. Is there any options by which the received frame quality can be improved by adjusting any VIP setting .Currently our VIP setting is ,  incoming embedded sync in Y(4:2:0)  is converted to  RGB  before putting into display buffer. Does it need VPE as well. Or it is purely dependent on the external Video Decoder.

With regards,

Jeyaseelan

  • 0
    TI__Guru**** 478015 points
    Jayaseelam,

    I am sorry, i could not get the fist question. Are you seeing 1 or 2 pixels at the start of every line? or at the end of the line?
    In any case, since you are using embedded sync, it all depends on where sync codes are placed in the line, so it depends on your decoder.
    One thing to try out, can you change pixel clock edge polarity in VIP?

    For second question, are you doing YUV to RGB conversion in the VIP path? In this case, CSC coefficients could affect the output quality slightly. Can you try changing CSC coefficients?

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    TI__Guru**** 478015 points
    Jayaseelam,

    I have not head back from you, so i am closing this thread.
    you could reopen this thread, if required.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Expert 1330 points
    Hi Brijesh,

    Black pixels are at the beginning only of every line only

    As per the datasheet of the external decoder only the HSB(Horizontal Syn=Begining) & HSE (Horizontal Sync = End) could be configured from I2C regarding Horizontal Sync timing. I configured the HSB /HSE to zero,still there is no effect on the display appearance. Also inverted the polarity of the Pixel Clock on the decoder side.Still no change in black pixels.

    Can you let me know on VIP side which register to configure the clock polarity. But i think pixel clocks are supplied from outside of the decoder.So is it required. Also the attached the timing diagram of the decoder.

    With regards,
    Jeyaseelan
  • 0 in reply to jeyaseelan kirubaharan
    TI__Guru**** 478015 points
    Hi Jayaseelan,

    can you try inverting PIXCLK_EDGE_POLARITY (bit10 in VIP_PORT register)? You could get the address of the VIP registers that you are using from the TRM..
    This is where we configure pixel clock edge polarity..

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Expert 1330 points
    Hi Brijesh ,

    It looks does not make much difference . I changed the Bit10 to 1 of register 0x4897 0004.Still the missing pixel issue is seen. on every line. Is there anything else could be changed from Jacinto side.

    Have attached the timing diagram also attached.



    With regards,

    Jeyaseelan
  • 0 in reply to jeyaseelan kirubaharan
    TI__Guru**** 478015 points

    Hi Jeyaseelan,

    There is nothing much that we can do from Jacinto as the embedded sync capture just depends on the input codes. If the codes are at correct place, it will capture correctly, otherwise, you might see these issues. I am assuming you did check in VIP that there are no errors reported.. 

    Can you check in your docoder? If there is anything in the decoder. 

    Are you seeing one or two pixel difference? Is it on all lines? Does it change on each line?

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 1330 points
    Hi Brijesh,

    Since i can not adjust either at VIP or from external decoder where this 2 pixel of horizontal blank is fixed,i have adjusted the capture area in the DDR to be preceeded by 2 pixel so that the display buffer (VID1) starts at the active video area. This could make only the active area visible.
    So now i can able to see only active video on the display. This may not be the right fix , but time being kept as work-around solution . Let me know if come across any other solution for removing horizontal(2-pixels)/vertical (2-3 lines) blanking for embedded sync. Meantime i will also check with decoder vendor if there any option available to remove those blanking .

    With regards,
    Jeyaseelan
  • 0 in reply to jeyaseelan kirubaharan
    TI__Guru**** 478015 points
    Jeyaseelan,

    By any chance, is there any interference in data lines path, which can cause shift/delay in the few data lines? or may be in the HSYNC line?

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Expert 1330 points
    Hi Brijesh,

    How can we check the errors or distortion in the data path of the video. Typical vide0 path is VIP->VPDMA->DDR. List Complete is used for triggering the interrupt to inform processor that 1 field has been transferred from VPDAMA -> DDR. Is there a way to check errors or delays in individual lines in VIP or VPDMA?

    With regards,
    Jeyaseelan
  • 0 in reply to jeyaseelan kirubaharan
    TI__Guru**** 478015 points
    Hi Jeyaseelan,

    I was talking about the interference on the data lines, not of the VIP to DDR path.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Expert 1330 points
    Hi Brijesh,

    I measured with scope one of the data lines P0 (P0-P7).The signal pattern looks the same for every cycle. So i assume physical signal looks ok. So feel this issue could be with external decoder line. Since i do not have time now , i will check on the same when get time.

    With regards,
    Jeyaseelan
  • 0 in reply to jeyaseelan kirubaharan
    TI__Guru**** 478015 points
    Thanks for the update Jeyaseelan.