Security Accelerator Debug Register Definitions

Hi,

I have investigation security accelerator problems. (hangs or incorrect encoding) I have found Core dump function (Sa_coreDump()) and debug register area (sa_collect_debug_info()) on Scratch RAM 0 (SRAM0) in LLD driver. I have not found any documentation of this section.

What is the definition of PDSP_IGP and PDSP_ICTE debug register area? (CSL_Cp_acePdsp_debugRegs) 

/**************************************************************************\
* Register Overlay Structure for PDSP_DEBUG
\**************************************************************************/
typedef struct {
volatile Uint32 PDSP_IGP[32]; /* PDSP Internal General Purpose Register */
volatile Uint32 PDSP_ICTE[32]; /* PDSP Internal Contants Table Entry Register */
} CSL_Cp_acePdsp_debugRegs; /* PDSP Debug Registers */

Devices : TCI6638K2K and 66AK2E05

MCSDK: pdk_k2e_4_0_8 and pdk_k2hk_4_0_8