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Original question:

CCS/66AK2H12: Keystone2 General perpose header format on SPI boot

CCS/66AK2H12: SPI boot up fail debug

Kz777
Expert 7895 points

Part Number: 66AK2H12

Tool/software: Code Composer Studio

Hi Champs,

We still have failed based on SPI boot.

Here is step

1:Write include GP header program to NOR Flash. Boot is failing.

2: When we look into JTAG, PC will stop by PC=0x00000128 or 0x00000138.

This address are is internal ROM area.

<Question 1>

So, Could you please tell us what kind of program is running at 0x00000128 or 0x00000138 ?

<Question2>

For debug this issue ,Could you please provide us following RBL address information ?

*Could you please provide RBL address for reading "Block0 Length"  on the GP header ?

*Could you please provide RBL address for reading "Block0  Base Address"  on the GP header ?

*Could you please provide RBL address for branching Block0 Base Address" that is after completing  GP format file read ?

Regards,

Kz777

 

  • 0
    TI__Guru** 116840 points

    We can`t share the ROM symbol table on E2E as this devices supports secure booting and the ROM symbol table contains reference to secure ROM symbols as well. Also, the symbol location will depend on silicon version so please indicate the silicon version. The failure in PG3.0 and PG 3.1 points to a reset vector. Is there any SPI reads observed on scope between SPI NOR flash and K2H SPI pins.

    Can you also indicate the value of DEVSTAT register on reset and if this is observed on multiple boards? Is this an image you can test on the TI EVM to make sure it is booting. This will eliminate any HW issue related to Power sequencing, boot pins, interface with SPI flash, boot image format or any other noise in the custom setup that may be contributing to this fail.

    Regards,
    Rahul