AM3352: AIN2 seems to be broken because of our connection in schematics

Thank you for this answer! I will check removing this capacitor. The error rate is 1 of 10 that reads wrong value. So i need to find this one again.

Concerning U1:C8 U1:A10 and U1:A12 is it ok to have them grounded directly? Reading the errata i got the feeling that leave them not connected.

From attached errata:
"TSC_ADC AIN terminals not used:
The preferred option is to have each unused AIN terminal connected to VSSA_ADC
through a 500-Ω resistor. Another option would be to leave the unused"

/Per

But we are in difficult situation. We have 1852 pcb in stock there U1:C8 U1:A10 and U1:A12 are connected to GND. We will cut this connection off if there is a problem having them so. On so many PCB it is risky expensive and time consuming to make this change. Our third part manufacturer Scanfil will drill this connection off if this is a must. It is better that you interpret the errata if we are forced to do it. Thanks for the support and the quick replies! /Per

Don’t worry about the pins being connected to ground for now.

 

Please provide more details that explain why you think there is an issue with AIN2.

 

Your schematic does not provide any connectivity details related to AIN0 and AIN3. Can you provide snapshots of circuits sourcing these inputs?

 

There is two advisories related to ADC in the Silicon Errata. You do not need to be concerned with 1.0.31 since you are not using the ADC as touch screen controller. The other advisory may apply, but I cannot tell without knowing what sources AIN0 and AIN3. I will wait and comment after you provide more information.

 

What clock rate are you operating the ADC. You may encounter a problem if you are operating the ADC with a slow clock. You should target an ADC clock of 3MHz.

 

Regards,

Paul

AIN0-7 AM3352.pdfThanks  for the answer!

Attached is all connection to AIN0-7 AM3352.

I will check the ADC clock with the software engineer.

Should i remove filter cap C193 and C194 as suggested in earlier response above?

Per Fager

Hello again.
Checked with our SW engineer. It seems to be 100kHz during the bootloader phase.
The AIN6 is read during this phase. The HW revision. So maybe the fault is here.
The AIN0 to AIN3 is 3MHz read after the Boot sequence.
I will come back if this works now or not.
Thank you!

I do not think the capacitors are causing any problem. They create a low-pass filter which should help eliminate noise from your measurement. The filter will slow the response time of the source, but I suspect this not a problem for your application.

Another customer recently reported an issue where the ADC was not measuring the correct voltage. We found they were using a 24 kHz ADC clock and needed to increase it to 500 kHz to eliminate the issue.

As you slow the ADC clock frequency, more time is inserted between each state of the ADC conversion process which allows leakage to affect the charge stored on internal sampling capacitors. This was influencing the measurement of the ADC.

Advisory 1.0.32 recommends connecting 500 ohm resistors to ground on unused connections to limit current through the unexpected paths that occur during power-up. Our analysis of the issue indicated internal resistance of the switch would limit current to an acceptable level, but we preferred the additional margin provided by the 500 ohm external resistor. Therefore, we do not expect a problem it they are shorted to ground, but recommend you add them in the next PCB revision.

I have another concern after reviewing the AIN0 and AIN3 sources. The ADC inputs are not fail-safe, so your design should not source any potential to the ADC inputs before the ADC power supply is valid. This requirement is defined in the Absolute Maximum Ratings parameter “Steady state max voltage at all I/O pins” where the limit is “-0.5V to I/O supply voltage + 0.3V”. It looks like the sources connected to AIN0 and AIN3 may apply a potential before the ADC supply is valid.

Regards,
Paul

Thanks for the answer!

But it didnt help. Since it works on all other besides two more cases we suspect that AM3352 has been internally partly broken.

We have six other modules out of a 50 batch that is totally broken. Shortcut within AM3352 on four supply voltages.

So i have been looking into other possibilities that can cause the problem. ESD or bad construction on the USB part of the schematic Can you please take a look on attached schematics? Two schematics one as it is today the other is a suggestion for a new solution.

Best Regards

Per Fager

NIBE AB

8863.ESD problem or Construction fault around AM3352.docx

I agree, it sounds like you have something in your system producing Electrical Over-Stress (EOS) events if you have multiple devices experiencing shorts between power supply pins.

 

I have seen similar cases occur when power is applied to a PCB assembly before ground. This is commonly called late voltage-ground (VG).

 

Here is an example of what can happen. You connect some of the processor pins to other circuits that are referenced to another ground or earth ground. This could be as simple as connecting a scope probe to a signal. However, you do not bond the PCB ground to the same ground as the other circuits before hot plugging the DC plug. The construction of the DC plug allows the positive terminal to make connection before the negative. If the DC power supply output is not isolated, the entire PCB rises to 12 volts relative to earth ground because the power supply ground is not connected yet. When this occurs the processor pins connected to external circuits may see a negative 12 volt potential relative to the PCB ground. This is very likely going to damage the processor pins. I realize the period of time where the positive terminal of the DC plug is attached while the negative not attached is fairly short, but it is more than long enough to create EOS event to the processor.

 

Regards,

Paul