Linux/AM5728: EDMA transfer from PCIe to DDR3 via EDMA

Hello!
It looks like PCIe party on FPGA side is serving PIO requests only. As I know, Xilinx provide PCIe IP Core with simple PIO example, which many developers stop with. It is responsibility of the user to develop a solution, capable to handle multi-dword payload/request. So in this case I'd first check, what is there on FPGA side.

Hi, Miyazaki,

Could you check as rrlagic suggested? Thanks!

Rex

Hello, Rex and rrlagic,

Thanks for your advice.

I’d like to request our customer to check FPGA side. I believe it takes time.　When I will receive customer’s feedback, please let me share it with you as soon as possible.

Best regards,　Miyazaki

Hello, Rex and rrlagic,

I got feedback from our customer. I shared customer’s issue incorrectly with you. I’m sorry, Please allow me to correct it. The direction of data-transfer was completely opposide. I mean, customer is evaluating EDMA as follows.

   DDR3 -->AM5728(RC with EDMA function) ----PCIe----> FPGA (Endpoint /ALTERA) board--->DDR4

Customer was evaluating EDMA with several Tx data size, however, it seems EDMA is not able to handle more than 4byte size.

Also, regarding this FPGA board(EP), customer connected this one to PC(Root Complex). And then, customer confirmed there was not any problem when they tried to do similar way. It means, we believe there is not any issue in FPGA board side, so, customer supposes there are some lack of EDMA/PCIe register setting.

For PCIe traffic between AM5728 and FPGA, since customer does not have PCIe protocol analyzer, we were not able to confirm if AM5728 was transferring data correctly or not.

It is really appreciated if you would be able to share reference-code, file, or helpful URL which related EDMA/PCIe register setting with us.

Best regards,

Miyazaki

Hello!

Transaction Layer packet (TLP) may have 3 or 4 DWORD header and variable payload. When processor initiates read or write, TLP payload is always 1 DWORD. On read request also 1 DWORD is requested. When processor initiates read or write, that is Programmable I/O, PIO. It is baseline design for FPGA side as well, and has very limited throughput because of overhead. To utilize the link, one needs do make multi-DWORD TLPs. Processors cannot do that, DMA engine can. In your case EDMA engine can make multi-dword TLP. Hoewever, it is important that FPGA internals also could handle multi-dword TLPs. It appears that your design does not. What I saw in references, baseline design treats all TLPs as one-dword and thus you see just 4 bytes served. There are IPs to have DMA on FPGA side, but I saw no references with slave capability to  serve DMA requests from RC. I had to develop my own.

So once again, one have to make sure FPGA design can handle multi-dword TLPs.

Hello rrlagic,

Thank you for your Expert’s experience and comments. I understand. I’m requesting customer to investigate it. Now, our customer is requesting FPGA maker to check it again. When I’ll be able to receive feedback about this, I’ll share it with you as soon as possible.

 

Best regards,

Miyazaki