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Original question:

Keystone 2 EMIF16: Is a 32-bit transaction "atomic" on the external interface?

RTOS/TMS320C6678: C6678 read data from FPGA through EMIF16 with a very low speed

user1741672
Prodigy 50 points
Part Number: TMS320C6678

Tool/software: TI-RTOS

In my application, C6678 read a lot of data from FPGA through EMIF16. I configure the read time as 5 EMIF clock cycles. It costs 5 cycles with one read as I configured. 

But there are about 20 cycles between the two READ actions.  This cause the average read speed is very low.  

Between the WRITE actions, there are no the extra cycles.  And  the write the speed is high.

How to eliminate the extra the 20 cycles between the READ actions? 

Read(5cycles)---(20cycles)---Read(5cycles)---(20cycles)---Read(5cycles)---(20cycles)---Read(5cycles)  

  • 0
    TI__Guru* 95265 points
    Hi,

    Do you have the EMIF initialization code to share here? How do you measure the gaps?

    Regards, Eric
  • 0 in reply to lding
    Prodigy 50 points

    Hi, Eric

    Thanks for your reply. The initialization code is here.

    void EMIFASetup(void)
{
    //Because the initial value is  0x3FFFFFFC.  Fisrst of all,  set it to zero.
    HWREG(SOC_EMIFA_0_REGS + EMIFA_CE5CFG) = 0;

    // This sentense is from a file: Keystone-I Alert - EMIF16 Performance degradation for asynchronous access
    // This sentense is usefull for WRITE operation. Not usefull for READ operation.  Why? 
    *(Uint32*)0x20c00008 |= 0x80000000;

    /* data width 16bit */
    EMIFAAsyncDevDataBusWidthSelect(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_3,
                                       EMIFA_DATA_BUSWITTH_16BIT);

    /* select Normal mode */
    EMIFAAsyncDevOpModeSelect(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_3,
                               EMIFA_ASYNC_INTERFACE_NORMAL_MODE);

    /* disable Extended WAIT */
    EMIFAExtendedWaitConfig(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_3,
                             EMIFA_EXTENDED_WAIT_DISABLE);

    /* Configure W_SETUP/R_SETUP W_STROBE/R_STROBE W_HOLD/R_HOLD  */
    /* wset, wstb, whld, rset, rstb, rhld, ta */
    EMIFAWaitTimingConfig(SOC_EMIFA_0_REGS, EMIFA_CHIP_SELECT_3,
                           EMIFA_ASYNC_WAITTIME_CONFIG(1, 3, 1, 1, 3, 1, 0));
}

    I measure the gaps from FPGA chip through the SignalTap II Logic Analyzer.  This software is in the Quartus II.

  • 0 in reply to user1741672
    TI__Guru* 95265 points
    Hi,

    Thanks for sharing this code! Can you let me know where those functions are defined or implemented? Are they part of TI Processor SDK RTOS for C667x (e.g. pdk_c667x_2_0_xx)? I didn't find them. Thanks for explanation.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 50 points

    Hi Eric

    I define the functions myself.

    Thanks.

  • 0 in reply to lding
    Prodigy 50 points

    Can you tell me how to write the initialization code with TI's library?

  • 0 in reply to user1741672
    TI__Mastermind 42545 points

    Hi,
    EMIF16 does have some delay through the internal switches within device. This delay can't be programmed similar to the delays associated with the external access but it can be minimized by adjusting how you access the EMIF16. There are a couple good E2E post that have explored this issue and I have attached links to those posts below.
    e2e.ti.com/.../337478
    e2e.ti.com/.../192245
    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 50 points

    Hi, Bill

    Thanks for your help.  I face the same problem with https://e2e.ti.com/support/processors/f/791/t/192245.  And  *(Uint32*)0x20C00008 |= 0x80000000; // Disable unused internal EMIF feature  has been used in my program. But it is not effective to the read operations.

    I still have two questions to confirm.

    1, *(Uint32*)0x20c00008 |= 0x80000000;  this sentense is only effective to the write operation.  It is not effective to the read operation. Is my understanding right?

    2, Now the extra delays between the two read operations can not be eliminated.  Is my understanding right?

    Thanks.

  • 0 in reply to user1741672
    TI__Mastermind 42545 points
    Hi,
    Based on my understanding, the disable of the unused EMIF function eliminates a periodic block to the EMIF interface. I think that block would effect both reads and writes.
    The extra delay between read operations cannot be programmed. It can be affected by the internal operation of the part. As noted in the other post, the use of EDMA has an effect compared to individual reads and writes as well as reading as a full 32bit word as opposed to 16bits half words. These effects will be limited. The interface was not designed to stream data at high speed so there will be some delay.
    Regards, Bill